Nanotip electrode non-volatile memory resistor cell

Abstract

A non-volatile memory resistor cell with a nanotip electrode, and corresponding fabrication method are provided. The method comprises: forming a first electrode with nanotips; forming a memory resistor material adjacent the nanotips; and, forming a second electrode adjacent the memory resistor material, where the memory resistor material is interposed between the first and second electrodes. Typically, the nanotips are iridium oxide (IrOx) and have a tip base size of about 50 nanometers, or less, a tip height in the range of 5 to 50 nm, and a nanotip density of greater than 100 nanotips per square micrometer. In one aspect, the substrate material can be silicon, silicon oxide, silicon nitride, or a noble metal. A metalorganic chemical vapor deposition (MOCVD) process is used to deposit Ir. The IrOx nanotips are grown from the deposited Ir.

1 - 28 . (canceled)  
   
   
       29 . A nanotip electrode non-volatile memory resistor cell, the memory cell comprising: 
 a first electrode with nanotips;    memory resistor material adjacent the nanotips; and    a second electrode adjacent the memory resistor material, where the memory resistor material is interposed between the first and second electrodes.    
   
   
       30 . The memory cell of  claim 29  wherein the first electrode nanotips have a tip base size of about 50 nanometers, or less.  
   
   
       31 . The memory cell of  claim 29  wherein the first electrode nanotips have a tip height in the range of 5 to 50 nm.  
   
   
       32 . The memory cell of  claim 29  wherein the first electrode nanotips have a nanotip density of greater than 100 nanotips per square micrometer.  
   
   
       33 . The memory cell of  claim 29  wherein the first electrode nanotips are made from iridium oxide (IrOx).  
   
   
       34 . The memory cell of  claim 33  further comprising: 
 a substrate;    a refractory metal film interposed between the substrate and the first electrode.    
   
   
       35 . The memory cell of  claim 29  further comprising: 
 a substrate, made from a material selected from the group including silicon, silicon oxide, silicon nitride, and noble metals; and    wherein the first electrode is formed adjacent the substrate.    
   
   
       36 . The memory cell of  claim 29  wherein the memory resistor material is a material selected from the group including Pr 0.3 Ca 0.7 MnO 3  (PCMO), colossal magnetoresistive (CMR) film, transition metal oxides, Mott insulators, and high-temperature super conductor (HTSC) material.  
   
   
       37 . The memory cell of  claim 29  wherein the first electrode nanotips have ends; and 
 wherein the memory resistor material has a thickness, between the first electrode nanotip ends and the second electrode, in the range of 30 to 200 nm.    
   
   
       38 . The memory cell of  claim 29  wherein the second electrode is a material selected from the group including Pt, refractory metals, refractory metal oxides, refractory metal nitrides, and A 1 .  
   
   
       39 . The memory cell of  claim 29  wherein the memory resistor material is adjacent to the nanotips in a relationship selected from the group including on the nanotips, surrounding the nanotips, and between the nanotips.