Method and apparatus for evaluating and optimizing a signaling system

Abstract

A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.

1 . A circuit comprising: 
 a semiconductor chip;    a transmit circuit disposed on the semiconductor chip, the transmit circuit to generate an output signal using a parameter having a value, the output signal having a first sequence of symbols;    a receive circuit disposed on the semiconductor chip, the receive circuit to receive the first sequence of symbols and to generate a first received sequence of symbols; and    a comparison circuit disposed on the semiconductor ship, the comparison circuit to compare the first sequence of symbols with the first received sequence of symbols to generate a comparison result, wherein the value of the parameter is adjustable.    
   
   
       2 . The circuit of  claim 1 , wherein each symbol comprises a single bit.  
   
   
       3 . The circuit of  claim 1 , wherein the circuit outputs the comparison result.  
   
   
       4 . The circuit of  claim 1 , wherein the circuit further outputs the value of the parameter.  
   
   
       5 . The circuit of  claim 1 , wherein the parameter is a timing parameter.  
   
   
       6 . The circuit of  claim 1 , wherein the parameter is selected from the group consisting of an output current reference, a crosstalk cancellation coefficient, and a self-equalization coefficient.  
   
   
       7 . A circuit comprising: 
 a semiconductor chip;    a transmit circuit disposed on the semiconductor chip, the transmit circuit to generate a first sequence of symbols while using a parameter set to a first value and to generate a second sequence of symbols while using the parameter set to a second value;    a receive circuit disposed on the semiconductor chip, the receive circuit to receive the first and second sequences of symbols and to generate respective first and second received sequences of symbols; and    a comparison circuit disposed on the semiconductor chip, the comparison circuit to compare the first sequence of symbols with the first received sequence of symbols to generate a first comparison result and to compare the second sequence of bits with the second received sequence of symbols to generate a second comparison result.    
   
   
       8 . The circuit of  claim 7 , wherein the circuit outputs the first and second comparison results.  
   
   
       9 . The circuit of  claim 8 , wherein the circuit further outputs the first and second values of the parameter.  
   
   
       10 . The circuit of  claim 7 , wherein the parameter is a timing parameter.  
   
   
       11 . A circuit comprising: 
 a semiconductor chip;    a transmit circuit disposed on the semiconductor chip, the transmit circuit to generate an output signal, the output signal having a first sequence of symbols;    a receive circuit disposed on the semiconductor chip, the receive circuit to receive the first sequence of symbols and generate a first received sequence of symbols using a parameter having a value; and    a comparison circuit disposed on the semiconductor chip, the comparison circuit to compare the first received sequence of symbols with a second sequence of symbols to generate a comparison result; wherein the value of the parameter is adjustable.    
   
   
       12 . The circuit of  claim 11 , wherein the parameter is a timing parameter.  
   
   
       13 . The circuit of  claim 11 , wherein the parameter is a voltage reference parameter.  
   
   
       14 . The circuit of  claim 11 , wherein the second sequence of symbols is related to the first sequence of symbols.  
   
   
       15 . The circuit of  claim 14 , wherein the second sequence of symbols is derived from the first sequence of symbols.  
   
   
       16 . The circuit of  claim 11 , wherein the circuit outputs the comparison result.  
   
   
       17 . The circuit of  claim 16 , wherein the circuits further outputs the value of the parameter.  
   
   
       18 . A circuit comprising: 
 a semiconductor chip;    a transmit circuit disposed on the semiconductor chip, the transmit circuit to generate a first output signal having first and second sequences of symbols;    a receive circuit disposed on the semiconductor chip, the receive circuit to receive the first sequence of symbols and to generate, while using a parameter that is set to a first value, a first received sequence of symbols and to receive the second sequence of symbols and to generate, while the parameter is set to a second value, a second received sequence of symbols; and    a comparison circuit disposed on the semiconductor chip, the comparison circuit to compare the first received sequence of symbols with a third sequence of symbols to generate a first comparison result and to compare the second received sequence of symbols with a forth sequence of symbols to generate a second comparison result.    
   
   
       19 . The circuit of  claim 18 , wherein the third sequence of symbols is related to the first sequence of symbols and the fourth sequence of symbols is related to the second sequence of symbols.  
   
   
       20 . The circuit of  claim 18 , wherein the parameter is a timing parameter.  
   
   
       21 . The circuit of  claim 18 , wherein the parameter is a voltage reference parameter.  
   
   
       22 . The circuit of  claim 18 , wherein the circuit outputs the first and second comparison results.  
   
   
       23 . The circuit of  claim 22 , wherein the circuit further outputs the first and second values of the parameter.  
   
   
       24 . The circuit of  claim 23 , wherein the third sequence of symbols is derived from the first sequence of symbols and the fourth sequence of symbols is derived from the second sequence of symbols.  
   
   
       25 . A circuit comprising: 
 a semiconductor chip;    a transmit circuit disposed on the semiconductor chip, the transmit circuit to generate a first output signal having first and second sequences of symbols;    a receive circuit disposed on the semiconductor chip, the receive circuit to receive the first sequence of symbols and to generate, while using a parameter that is set to a first value, a first received sequence of symbols, and to receive the second sequence of symbols and to generate, while the parameter is set to a second value, a second received sequence of symbols; and    a comparison circuit disposed on the semiconductor chip, the comparison circuit to compare the first received sequence of symbols with the first sequence of symbols to generate a first comparison result and to compare the second received sequence of symbols with the second sequence of symbols to generate a second comparison result.    
   
   
       26 . The circuit of  claim 25 , wherein the parameter is a timing parameter.  
   
   
       27 . The circuit of  claim 25 , wherein the parameter is a voltage reference parameter.  
   
   
       28 . The circuit of  claim 25 , wherein the circuit outputs the first and second comparison results.  
   
   
       29 . The circuit of  claim 28 , wherein the circuit further outputs the first and second values of the parameter.