Interconnection pattern design

Abstract

An interconnection pattern design, which has an improved reliability under mechanical shock and thermal cycling loads. A semiconductor component comprises a plurality of interconnections aligned into rows and columns to form an interconnection pattern, wherein the interconnections are aligned such that the pattern has substantially rounded or chamfered corners. The present invention provides an improved interconnection life and reliability of ball grid array packages and it is easily implemented.

1 . A semiconductor component comprising a plurality of interconnections aligned into rows and columns to form an interconnection pattern, wherein the interconnections are aligned such that the interconnection pattern has substantially rounded or chamfered corners, wherein the interconnection pattern comprises a first plurality of interconnections, which first interconnections are electrically connecting, and a second plurality of interconnections, which second interconnections are electrically non-connecting, on the periphery of the interconnection pattern and/or forming one or more angular or rectangular corners of the interconnection pattern, and wherein the second interconnections are relatively weaker than the first interconnections.  
   
   
       2 . A semiconductor component as claimed in  claim 1 , wherein the interconnection pattern is formed as a ball grid array in which at least two joints at each corner of the array are missing.  
   
   
       3 . A semiconductor component as claimed in  claim 1 , wherein the interconnection pattern is formed as a ball grid array in which at least the outermost rows and the outermost columns of the grid have fewer joints than the second outermost rows and the second outermost columns of the grid, and in which the second outermost rows and the second outermost columns of the grid have an equal number of or fewer joints than the third outermost rows and the third outermost columns of the grid.  
   
   
       4 . A semiconductor component as claimed in  claim 3 , wherein said joints are electrically connecting.  
   
   
       5 . A semiconductor component as claimed in  claim 1 , wherein a plurality of bonding joints are located about the periphery of the semiconductor component in an array arrangement, wherein the bonding joints are positioned in first, second and at least in one third loops, the first, second and third loops comprising respectively an outer loop, a middle loop, and an inner loop along the sides of the semiconductor component, the joints in the outer loop being positioned such that the outer loop has substantially rounded or chamfered corners.  
   
   
       6 . A semiconductor component comprising a plurality of interconnections aligned into rows and columns to form an interconnection pattern, wherein the interconnections are aligned such that the interconnection pattern has substantially rounded or chamfered corners, wherein the interconnection pattern comprises a plurality of first interconnections, which first interconnections are electrically connecting, and a plurality of second interconnections, which second interconnections are electrically non-connecting, wherein the second interconnections are on the periphery of the interconnection pattern, and wherein the second interconnections are relatively weaker than the first interconnections.  
   
   
       7 . A semiconductor component comprising a plurality of interconnections aligned into rows and columns to form an interconnection pattern, wherein the interconnections are aligned such that the interconnection pattern has substantially rounded or chamfered corners, wherein the interconnection pattern comprises a plurality of first interconnections, which first interconnections are electrically connecting, and a plurality of second interconnections, which second interconnections are electrically non-connecting, wherein the second interconnections form one or more angular or rectangular corners of the interconnection pattern, and wherein the second interconnections are relatively weaker than the first interconnections.  
   
   
       8 . A semiconductor device comprising at least one printed wiring board (PWB) and at least one semiconductor component bonded to the PWB, wherein interconnections formed as an interconnection pattern between the PWB and at least one semiconductor component are aligned such that the interconnection pattern has substantially rounded or chamfered corners, wherein the interconnection pattern comprises a first plurality of interconnections, which first interconnections are electrically connecting, and a second plurality of interconnections, which second interconnections are electrically non-connecting, on the periphery of the interconnection pattern and/or forming one or more angular or rectangular corners of the interconnection pattern, wherein the second interconnections are relatively weaker than the first interconnections.  
   
   
       9 . A semiconductor device as claimed in  claim 8 , wherein the semiconductor device is a portable device.  
   
   
       10 . A semiconductor device as claimed in  claim 8 , wherein the interconnection pattern is formed as a ball grid array in which at least two joints at each corner of the array are missing.  
   
   
       11 . A semiconductor device as claimed in  claim 8 , wherein the interconnection pattern is formed as a ball grid in which at least the outermost rows and the outermost columns of the grid have fewer joints than the second outermost rows and the second outermost columns of the grid, and in which the second outermost rows and the second outermost columns of the grid have an equal number of or fewer joints than the third outermost rows and the third outermost columns of the grid.  
   
   
       12 . A semiconductor device as claimed in  claim 11 , wherein said joints are electrically connecting.  
   
   
       13 . A semiconductor device as claimed in  claim 8 , wherein a plurality of bonding joints are located about the periphery of the semiconductor component in an array arrangement, wherein the bonding joints are positioned in first, second and at least one third loops, the first, second and third loops comprising respectively an outer loop, a middle loop, and an inner loop along the sides of the semiconductor component, the joints in the outer loop being positioned such that the outer loop has substantially rounded or chamfered corners.  
   
   
       14 . A semiconductor device comprising at least one printed wiring board (PWB) and at least one semiconductor component bonded to the PWB, wherein interconnections formed as an interconnection pattern between the PWB and at least one semiconductor component are aligned such that the interconnection pattern has substantially rounded or chamfered corners, wherein the interconnection pattern comprises a plurality of first interconnections, which first interconnections are electrically connecting, and a plurality of second interconnections, which second interconnections are electrically non-connecting, wherein the second interconnections are on the periphery of the interconnection pattern, and wherein the second interconnections are relatively weaker than the first interconnections.  
   
   
       15 . A semiconductor device comprising at least one printed wiring board (PWB) and at least one semiconductor component bonded to the PWB, wherein interconnections formed as an interconnection pattern between the PWB and at least one semiconductor component are aligned such that the interconnection pattern has substantially rounded or chamfered corners, wherein the interconnection pattern comprises a plurality of first interconnections, which first interconnections are electrically connecting, and a plurality of second interconnections, which second interconnections are electrically non-connecting, wherein the second interconnections form one or more angular or rectangular corners of the interconnection pattern, and wherein the second interconnections are relatively weaker than the first interconnections.