Three-dimensional multi-gate device and fabricating method thereof

Abstract

A three-dimensional multi-gate device has a silicon fin, a gate structure, and a stress-adjusting layer. The gate structure contacts with three surface of the silicon fin to form a three-dimensional gate structure. The stress-adjusting layer is disposed on the gate structure to provide stress along the direction parallel to the channel length of the gate structure. The stress helps promote the mobility of the charges in the channel region under the gate structure and improve the electrical performance such as drive current and DIBL of the three-dimensional multi-gate device.

1 . A three-dimensional multi-gate device comprising: 
 a semiconductor substrate;    a silicon fin disposed on the semiconductor substrate, the silicon fin having a top surface and two side surfaces;    a gate structure disposed on the silicon fin and partially covering the top surface and the two side surfaces of the silicon fin;    two doped regions disposed in the silicon fin under both sides of the gate structure; and    a stress-adjusting layer covering the gate structure.    
   
   
       2 . The three-dimensional multi-gate device of  claim 1 , further comprising a plurality of salicide layers disposed on the gate structure and the two doped regions.  
   
   
       3 . The three-dimensional multi-gate device of  claim 1 , wherein the salicide layers comprise cobalt salicide layers, nickel salicide layers, titanium salicide layers or platinum salicide layers.  
   
   
       4 . The three-dimensional multi-gate device of  claim 1 , wherein the stress-adjusting layer comprises a silicon nitride layer, a silicon oxide layer or a silicon oxynitride layer.  
   
   
       5 . The three-dimensional multi-gate device of  claim 1 , wherein the stress-adjusting layer has a thickness ranging between 100 Å to 2000 Å.  
   
   
       6 . The three-dimensional multi-gate device of  claim 1 , further comprising a dielectric layer disposed on the stress-adjusting layer.  
   
   
       7 . The three-dimensional multi-gate device of  claim 1 , further comprising a plurality of via holes passing through the dielectric layer and the stress-adjusting layer.  
   
   
       8 . The three-dimensional multi-gate device of  claim 1 , wherein the three-dimensional multi-gate device is N type, and the stress-adjusting layer provides a tensile stress.  
   
   
       9 . The three-dimensional multi-gate device of  claim 1 , wherein the three-dimensional multi-gate device is P type, and the stress-adjusting layer provides a compressed stress.