Housing for electronic components

Abstract

A housing is formed in such a way that a plurality of chip trays each holding a plurality of semiconductor chips are stored in a storage tray, wherein the chip tray is formed by vertically connecting an upper unit and a lower unit, both of which have the same structure. The semiconductor chips are held between the upper unit and the lower unit of the chip tray, thus preventing two-dimensional movement thereof. When a plurality of housings each having the aforementioned structure are vertically combined together, a plurality of semiconductor chips can be further held between the upper unit of one housing and the lower unit of another housing. This makes it possible to simultaneously transport numerous semiconductor chips, whereby the semiconductor chips are each encapsulated in a surface mount chip package.

1 . A housing comprising: 
 at least one chip tray for holding a plurality of semiconductor chips; and    a storage tray for storing the at least one chip tray,    wherein the chip tray is formed by vertically connecting an upper unit and a lower unit, between which the plurality of semiconductor chips are held.    
   
   
       2 . A housing according to  claim 1 , wherein the chip tray is shaped in an appropriate size, which is completely held inside of the storage tray within its thickness.  
   
   
       3 . A housing according to  claim 1 , wherein the storage tray has a plurality of engagement portions, which realize engagement with the chip tray and which maintain a vertically connected state of the upper unit and the lower unit.  
   
   
       4 . A housing according to  claim 1 , wherein both of the upper unit and the lower unit have a same structure, so that the lower unit is covered with the upper unit.  
   
   
       5 . A housing according to  claim 1 , wherein when being vertically combined with another housing, a plurality of semiconductor chips are further held between the upper unit thereof and the lower unit of the other housing.  
   
   
       6 . A housing according to  claim 1 , wherein the plurality of semiconductor chips are each encapsulated in a surface mount chip package.  
   
   
       7 . A housing according to  claim 2 , wherein the storage tray has a plurality of engagement portions, which realize engagement with the chip tray and which maintain a vertically connected state of the upper unit and the lower unit.  
   
   
       8 . A housing according to  claim 2 , wherein both of the upper unit and the lower unit have a same structure, so that the lower unit is covered with the upper unit.  
   
   
       9 . A housing according to  claim 2 , wherein when being vertically combined with another housing, a plurality of semiconductor chips are further held between the upper unit thereof and the lower unit of the other housing.  
   
   
       10 . A housing according to  claim 2 , wherein the plurality of semiconductor chips are each encapsulated in a surface mount chip package.