Memory controller and memory control method

Abstract

A memory controller has a control unit receiving a transfer data from a transmission circuit and executing a burst transfer of the transfer data to a reception circuit. The transmission circuit transmits a first data of a first bit length for a first burst times by a burst transmission. The amount of the transfer data is equal to a product of the first bit length and the first burst times. The reception circuit receives a second data of a second bit length for a second burst times by a burst reception. When the amount of the first data received by the control unit becomes equal to or more than a product of the second bit length and the second burst times, the control unit transfers the received first data as the second data to the reception circuit, regardless of the number of the first data received by the control unit.

1 . A memory controller comprising: 
 a control unit configured to receive a transfer data from a transmission circuit and execute a burst transfer of said transfer data to a reception circuit, wherein said transmission circuit transmits a first data of a first bit length for a first burst times by a burst transmission, an amount of said transfer data from said transmission circuit is equal to a product of said first bit length and said first burst times, and said reception circuit receives a second data of a second bit length for a second burst times by a burst reception; and    a data buffer configured to store said transfer data,    wherein when an amount of said first data received by said control unit becomes equal to or more than a product of said second bit length and said second burst times, said control unit transfers said received first data as said second data to said reception circuit, regardless of a number of said first data received by said control unit.    
     
     
         2 . The memory controller according to  claim 1 , further comprising a register configured to store information indicating said first bit length and said second bit length.  
     
     
         3 . The memory controller according to  claim 1 , further comprising an external terminal through which said first bit length and said second bit length are specified.  
     
     
         4 . A memory controller comprising: 
 a data buffer configured to store a transfer data of a first burst length, wherein said first burst length is specified for every burst transfer;    a command split circuit configured to split a command indicating a burst transfer with said first burst length into commands each indicating a burst transfer with a split burst length, in accordance with a predetermined second burst length supported by a memory and burst transferred in response to one command issuance;    a burst length table configured to store said split burst length; and    a burst timing control circuit configured to control a timing of a burst transfer of said transfer data such that said transfer data stored in said data buffer is burst transferred to said memory by said split burst length stored in said burst length table.    
     
     
         5 . The memory controller according to  claim 4 , 
 wherein when an amount of said transfer data stored in said data buffer becomes equal to or more than that corresponding to said split burst length, said burst timing control circuit initiates said burst transfer of said transfer data.    
     
     
         6 . The memory controller according to  claim 4 , 
 wherein when a start address of a destination of said transfer data is different from a burst boundary, said command split circuit specifies a data length from said start address to said burst boundary as said split burst length.    
     
     
         7 . The memory controller according to  claim 4 , 
 wherein said command split circuit determines said split burst length based on a first data width with which said transfer data is transmitted to said data buffer and a second data width with which said transfer data is transferred from said data buffer to said memory.    
     
     
         8 . The memory controller according to  claim 7 , further comprising a register configured to store information indicating said first data width and said second data width.  
     
     
         9 . The memory controller according to  claim 7 , further comprising an external terminal through which said first data width and said second data width are specified.  
     
     
         10 . A memory control method comprising: 
 (A) storing a transfer data of a first burst length in a data buffer, wherein said first burst length is specified for every burst transfer;    (B) splitting a command indicating a burst transfer with said first burst length into commands each indicating a burst transfer with a split burst length, in accordance with a predetermined second burst length supported by a memory and burst transferred in response to one command issuance;    (C) storing said split burst length in a burst length table; and    (D) controlling a timing of a burst transfer of said transfer data such that said transfer data stored in said data buffer is burst transferred to said memory by said split burst length stored in said burst length table.    
     
     
         11 . The memory control method according to  claim 10 , 
 wherein when an amount of said transfer data stored in said data buffer during said (A) step becomes equal to or more than that corresponding to said split burst length, said burst transfer of said transfer data is initiated in accordance with said (D) step.    
     
     
         12 . The memory control method according to  claim 10 , 
 wherein in said (B) step, when a start address of a destination of said transfer data is different from a burst boundary, a data length from said start address to said burst boundary is specified as said split burst length.    
     
     
         13 . The memory control method according to  claim 10 , 
 wherein in said (B) step, said split burst length is determined based on a first data width with which said transfer data is transmitted to said data buffer and a second data width with which said transfer data is transferred from said data buffer to said memory.    
     
     
         14 . The memory control method according to  claim 13 , further comprising: (E) externally specifying said first data width and said second data width.