High k gate stack on III-V compound semiconductors

Abstract

A method of forming a high k gate stack (dielectric constant of greater than that of silicon dioxide) on a surface of a III-V compound semiconductor, such GaAs, is provided. The method includes subjecting a III-V compound semiconductor material to a precleaning process which removes native oxides from a surface of the III-V compound semiconductor material; forming a semiconductor, e.g., amorphous Si, layer in-situ on the cleaned surface of the III-V compound semiconductor material; and forming a dielectric material having a dielectric constant that is greater than silicon dioxide on the semiconducting layer. In some embodiments, the semiconducting layer is partially or completely converted into a layer including at least a surface layer that is comprised of AO x N y prior to forming the dielectric material. In accordance with the present invention, A is a semiconducting material, preferably Si, x is 0 to 1, y is 0 to 1 and x and y are both not zero.

1 . A method of forming a material stack on a III-V compound semiconductor comprising: 
 removing native oxides from a III-V compound semiconductor material to provide a treated surface;    forming a semiconducting layer in-situ on said treated surface of said III-V compound semiconductor material; and    forming a dielectric material having a dielectric constant that is greater than silicon dioxide on said semiconducting layer.    
   
   
       2 . The method of  claim 1  wherein said removing said native oxides comprises desorption at a temperature of about 600° C. or greater.  
   
   
       3 . The method of  claim 1  wherein said removing said native oxides comprises a plasma H process.  
   
   
       4 . The method of  claim 1  wherein said semiconducting layer is formed by epitaxy.  
   
   
       5 . The method of  claim 1  further comprising completely or partially converting the semiconducting layer into a AO x N y  layer, wherein A is a semiconducting material, x is 0 to 1, y is 0 to 1 and x and y are both not zero, prior to forming the dielectric material.  
   
   
       6 . The method of  claim 1  wherein each of said steps is performed in-situ.  
   
   
       7 . The method of  claim 1  wherein each of said steps is performed at a temperature of less than 300° C.  
   
   
       8 . A method of forming a material stack on a III-V compound semiconductor comprising: 
 removing native oxides from a III-V compound semiconductor material to provide a treated surface;    forming a semiconducting layer in-situ on said treated surface of said III-V compound semiconductor material;    converting at least an upper surface region of said semiconducting layer to a region comprised of AO x N y  wherein A is a semiconducting material, x is from 0 to 1, y is from 0 to 1 and x and y are both not zero; and    forming a dielectric material having a dielectric constant that is greater than silicon dioxide on the upper surface region of said semiconducting layer.    
   
   
       9 . The method of  claim 8  wherein said removing said native oxides comprises desorption at a temperature of about 600° C. or greater.  
   
   
       10 . The method of  claim 8  wherein said removing said native oxides comprises a plasma H process.  
   
   
       11 . The method of  claim 8  wherein said semiconducting layer formed by epitaxy.  
   
   
       12 . The method of  claim 8  wherein each of said steps is performed in-situ.  
   
   
       13 . The method of  claim 8  wherein each of said steps is performed at a temperature of less than 300° C.  
   
   
       14 . A semiconductor structure comprising: 
 a III-V compound semiconductor material having a surface that is essentially free of oxides;    a semiconducting layer located on said surface, wherein an interface is present between the III-V compound semiconductor material and the semiconducting layer that has an interface state density of about 10 12  cm −2  eV −1  or less; and    a dielectric material having dielectric constant greater than that of silicon dioxide located on said semiconducting layer.    
   
   
       15 . The semiconductor structure of  claim 14  wherein said III-V compound semiconductor material includes an upper layer and a lower layer, wherein said upper layer has a wider-band gap than said lower layer.  
   
   
       16 . The semiconductor structure of  claim 14  wherein said semiconducting layer is amorphous.  
   
   
       17 . The semiconductor structure of  claim 14  wherein said semiconducting layer is Si.  
   
   
       18 . The semiconductor structure of  claim 14  wherein said semiconducting layer includes at least a surface region of AO x N y  wherein A is a semiconducting material, x is from 0 to 1, y is from 0 to 1, both x and y are not zero and said dielectric material is located on said surface region of AO x N y .  
   
   
       19 . The semiconductor structure of  claim 14  wherein said semiconducting layer is replaced completely by an AO x N y  layer wherein A is a semiconducting material, x is from 0 to 1 and y is from 0 to 1 and said dielectric material is located on said AO x N y  layer.  
   
   
       20 . The semiconductor structure of  claim 14  wherein said dielectric material is a Hf-based dielectric.  
   
   
       21 . The semiconductor structure of  claim 14  further comprising an electrode or electrode stack on said dielectric material.  
   
   
       22 . The semiconductor structure of  claim 14  wherein said dielectric material is a gate dielectric of at least one field effect transistor device.  
   
   
       23 . A method of enhancing the activation of implanted dopants within a III/V compound semiconductor material comprising: 
 providing a semiconducting cap layer atop a III/V compound semiconductor that has a surface that is essentially free of oxides, said III/V compound semiconductor including n-type dopants, p-type dopants or both; and    annealing the dopants to provide at least one activated dopant region in said III/V compound semiconductor.