US2007161206A1PendingUtilityA1

Isolation structure for strained channel transistors

Assignee: KO CHIH-HSINPriority: Apr 25, 2003Filed: Oct 26, 2006Published: Jul 12, 2007
Est. expiryApr 25, 2023(expired)· nominal 20-yr term from priority
H10W 10/17H10W 10/014H10D 84/0167H10D 84/0151H10D 84/0128H10D 30/797H10D 30/795H10D 30/751H10D 84/0188H10D 84/038H10D 30/798
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Claims

Abstract

A method and system is disclosed for forming an improved isolation structure for strained channel transistors. In one example, an isolation structure is formed comprising a trench filled with a nitrogen-containing liner and a gap filler. The nitrogen-containing liner enables the isolation structure to reduce compressive strain contribution to the channel region.

Claims

exact text as granted — not AI-modified
1 . A method for forming an isolation structure for strained channel transistors comprising: 
 forming a pattern mask over a semiconductor substrate;    forming a trench in the semiconductor substrate through the pattern mask;    forming a nitrogen-containing liner in the trench; and    filling the trench with a gap filler material,    wherein the nitrogen-containing liner reduces a compressive strain caused by the isolation structure.    
   
   
       2 . The method according to  claim 1 , wherein the trench is formed by an anisotropic plasma etching with fluorine chemistry.  
   
   
       3 . The method according to  claim 1 , wherein the nitrogen-containing liner is comprised of silicon nitride or silicon oxynitride.  
   
   
       4 . The method according to  claim 1 , wherein the nitrogen-containing liner has a nitrogen content of 5 to 60 percent (%).  
   
   
       5 . The method according to  claim 1 , wherein the nitrogen-containing liner has a thickness in the range of 10 to 500 angstroms.  
   
   
       6 . The method according to  claim 1 , wherein the nitrogen-containing liner is formed by a low-pressure chemical vapor deposition (LPCVD).  
   
   
       7 . The method according to  claim 6 , wherein the low-pressure chemical vapor deposition (LPCVD) uses precursor gases such as ammonia or silane.  
   
   
       8 . The method according to  claim 6 , wherein the low-pressure chemical vapor deposition (LPCVD) operates at a temperature between 500 and 900 degrees Celsius.  
   
   
       9 . The method according to  claim 1 , wherein the nitrogen-containing liner is a high tensile stress conformal nitride liner.  
   
   
       10 . The method according to  claim 1 , wherein the gap filler material is at least one of silicon oxide, CVD silicon oxide, or CVD poly-crystalline silicon.  
   
   
       11 . The method according to  claim 1 , further comprising, after filling the trench with the gap filler material, densifying the gap filler material by either a pyrogenic oxidation anneal or a conventional anneal process.  
   
   
       12 . The method according to  claim 1 , wherein the pyrogenic oxidation anneal process is conducted at a temperature of 800 degrees Celsius.  
   
   
       13 . The method according to  claim 1 , further comprising, after forming the trench, forming an oxide liner underlying the nitrogen-containing liner.  
   
   
       14 . The method according to  claim 13 , wherein the oxide liner is a silicon oxide liner.  
   
   
       15 . The method according to  claim 14 , wherein the step of forming the oxide liner is a chemical vapor deposition step or a thermal oxidation step.  
   
   
       16 . The method according to  claim 1 , further comprising the step, after the step of forming the trench: 
 widening the pattern mask by a predetermined pull-back portion; and    performing a corner rounding of the trench.    
   
   
       17 . The method according to  claim 16 , wherein the corner rounding step is an anneal at a temperature in the range of 700 to 950 degrees Celsius in a gaseous ambient.  
   
   
       18 . The method according to  claim 16 , further comprising a step, after the step of corner rounding, of forming a silicon oxide liner.  
   
   
       19 . The method according to  claim 16 , wherein the pull back portion is in the range of 50 to 1000 angstroms.  
   
   
       20 . The method according to  claim 16 , wherein the pull back portion is formed by a chemical treatment with a wet etch process.  
   
   
       21 . The method according to  claim 2 , wherein the patterned mask comprises a silicon nitride layer overlying a pad oxide layer.  
   
   
       22 . The method according to  claim 2 , further comprising, after filling the trench with the gap filler material, planarizing trench with the gap filler material and the pattern mask.  
   
   
       23 . The method according to  claim 12 , further comprising removing the pattern mask.  
   
   
       24 . The method according to  claim 2 , wherein a surface of the gap filler material is higher than two ends of the liner in the trench.  
   
   
       25 . A method for forming an isolation structure for strained channel transistors, the method comprising: 
 forming a pattern mask over a semiconductor substrate;    forming a trench in the semiconductor substrate through the pattern mask;    widening the pattern mask by a predetermined pull-back portion;    forming an oxide liner in the trench;    forming a nitrogen-containing liner on the oxide liner; and    filling the trench with a gap filler material,    wherein the nitrogen-containing liner reduces a compressive strain asserted by the gap filler material contained therein.    
   
   
       26 . The method according to  claim 25 , wherein the nitrogen-containing liner is comprised of silicon nitride or silicon oxynitride.  
   
   
       27 . The method according to  claim 25 , wherein the nitrogen-containing liner has a nitrogen content of 5 to 60 percent (%).  
   
   
       28 . The method according to  claim 25 , wherein the nitrogen-containing liner has a thickness in the range of 10 to 500 angstroms.  
   
   
       29 . The method according to  claim 25 , wherein forming the nitrogen-containing liner uses a low-pressure chemical vapor deposition (LPCVD).  
   
   
       30 . The method according to  claim 25 , further comprising, after filling the trench with the gap filler material, densifying the gap filler material by either a pyrogenic oxidation anneal or a conventional anneal process.  
   
   
       31 . The method according to  claim 25 , further comprising, wherein the oxide liner is a silicon oxide liner.  
   
   
       32 . The method according to  claim 25 , further comprising performing a corner rounding of the trench.  
   
   
       33 . The method according to  claim 25 , wherein the pull back portion is in the range of 50 to 1000 angstroms.  
   
   
       34 . The method according to  claim 25 , wherein the patterned mask comprises a silicon nitride layer overlying a pad oxide layer.  
   
   
       35 . The method according to  claim 25 , further comprising, after filling the trench with the gap filler material, planarizing the trench with the gap filler material and the pattern mask.  
   
   
       36 . The method according to  claim 35 , further comprising removing the pattern mask.  
   
   
       37 . The method according to  claim 25 , wherein a surface of the gap filler material is higher than two ends of the liner in the trench

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