Manufacturing CCDS in a conventional CMOS process

Abstract

A technique for forming Charge-Coupled Devices (CCDS) in a conventional Complementary Metal Oxide Semiconductor (CMOS) process. A number of single-layer polysilicon gates are formed on an as-grown, native doped silicon substrate, with gaps between them. Masking is used to selectively dope the gates while preventing doping of the silicon in the gaps. Masking may likewise be used to selectively silicide the gates while preventing silicide formation in the gaps. Conventional source-drain processing produces input/output diffusions for the CCD.

1 . A Charge-Coupled Device (CCD) formed by a Complementary Metal Oxide Semiconductor (CMOS) process comprising: 
 a substrate having a charge-carrying region;    a gate oxide layer on the charge-carrying region;    a plurality of single layer polysilicon gates on the gate oxide layer, deposited on the gate oxide layer, and patterned to define the individual single layer polysilicon gates and a plurality of gap regions therebetween; and    a dopant selectively applied into unmasked regions associated with each of the plurality of single layer polysilicon gates, wherein the masked regions prevent penetration of the dopants into the gap regions.    
     
     
         2 . The apparatus of  claim 1  wherein: 
 the single layer polysilicon gates are annealed to further spread the dopant through the single layer polysilicon gates.    
     
     
         3 . The apparatus of  claim 1  wherein the dopant is applied by ion implantation.  
     
     
         4 . The apparatus of  claim 1  wherein the dopant is a P-type for one or more of the polysilicon gates.  
     
     
         5 . The apparatus of  claim 1  wherein the dopant is an N-type for one or more of the polysilicon gates.  
     
     
         6 . The apparatus of  claim 1  wherein at least one masked region extends over at least a portion of the edge of at least one of the gates.  
     
     
         7 . The apparatus of  claim 1  additionally comprising one or more N- or P-type field-effect transistors elsewhere on the substrate.  
     
     
         8 . The apparatus of  claim 1  wherein a lightly doped as-grown substrate is used.  
     
     
         9 . The apparatus of  claim 1  additionally comprising an additional implant that is part of the CMOS process.  
     
     
         10 . The apparatus of  claim 9  wherein the additional implant is selected from the group consisting of a source-drain extension implant and a lightly-doped drain implant.  
     
     
         11 . The apparatus of  claim 1  wherein the polysilicon gates are formed in a dopant atmosphere.  
     
     
         12 . The apparatus of  claim 1  wherein a source/drain structure used for forming MOS transistors is placed adjacent at least one gate for injection or extraction of charge.  
     
     
         13 . The apparatus of  claim 1  additionally comprising: 
 additional in Complementary Metal Oxide Semiconductor (CMOS) circuits including NFETs and PFETs using the same substrate.    
     
     
         14 . The apparatus of  claim 1  additionally comprising: 
 a metal silicide region formed on at least one single-layer polysilicon gate.    
     
     
         15 . The apparatus of  claim 14  wherein a metal silicide pattern further prevents silicide formation in at least one of the gaps.  
     
     
         16 . The apparatus of  claim 14  additionally comprising a metal silicide pattern that defines resistors on the substrate.  
     
     
         17 . The apparatus of  claim 14  additionally wherein a metal silicide pattern further prevents silicide formation over at least a portion of the periphery of at least one of the gates.  
     
     
         18 . The apparatus of  claim 1  wherein one or more gates are sufficiently close together such that a source-drain-extension spacer insulator fills the gaps between gates, and such that silicide is formed on the gates but is not formed in the gaps.  
     
     
         19 . A Charge-Coupled Device (CCD) formed in a Complementary Metal Oxide Semiconductor (CMOS) process comprising: 
 a substrate having a charge-carrying region;    an as-grown, native doping level preserved on the substrate;    a gate oxide layer formed on the charge-carrying region; and    a plurality of single layer polysilicon gates, formed on the gate oxide layer, by depositing a polysilicon layer on the gate oxide layer and then patterning the polysilicon layer to define the individual single layer polysilicon gates and a plurality of gaps therebetween.    
     
     
         20 . The apparatus of  claim 19  additionally comprising: 
 masked regions and unmasked regions substantially aligned with the gaps and the gates, respectively; and    a dopant, selectively applied into the unmasked regions associated with each of the plurality of single layer polysilicon gates, wherein the masked regions prevent penetration of the implanting dopants into the gap regions.    
     
     
         21 . The apparatus of  claim 20  additionally wherein: 
 the single layer polysilicon gates are annealed to further spread the dopant through the single layer polysilicon gates.    
     
     
         22 . The apparatus of  claim 20  wherein the dopant is applied by ion implantation.  
     
     
         23 . The apparatus of  claim 20  wherein at least one masked region extends over at least a portion of the edge of at least one of the gates.  
     
     
         24 . The apparatus of  claim 20  additionally comprising one or more N- or P-type field-effect transistors located on the substrate.  
     
     
         25 . The apparatus of  claim 20  additionally comprising an implantation to prevent penetration of the gaps.  
     
     
         26 . The apparatus of  claim 25  wherein the implant is selected from the group consisting of a source-drain extension and a lightly-doped drain.  
     
     
         27 . The apparatus of  claim 19  wherein the polysilicon gates are formed in a dopant atmosphere.  
     
     
         28 . The apparatus of  claim 19  wherein a source/drain structure is placed adjacent at least one gate for injection or extraction of charge.  
     
     
         29 . The apparatus of  claim 19  additionally comprising: 
 one or more devices commonly used in Complementary Metal Oxide Semiconductor (CMOS) circuits formed on the same substrate, as the CCD device.