LDMOS Device and Method of Fabrication of LDMOS Device

Abstract

A lateral double diffused metal oxide semiconductor (LDMOS) device, and method of fabricating such a device, are provided. The method comprises the steps of: (a) providing a substrate of a first conductivity type; (b) forming within the substrate a well region of a second conductivity type, the well region having a super steep retrograde (SSR) well profile in which a doping concentration changes with depth so as to provide a lighter doping concentration in a surface region of the well region than in a region below the surface region of the well region; (c) forming a gate layer which partly overlies the well region and is insulated from the well region; and (d) forming one of a source region and a drain region in the well region. The presence of the SSR well region provides a lighter surface doping to enable a higher breakdown voltage to be obtained within the LDMOS device, and heavier sub-surface doping to decrease the on-resistance.

1 . A lateral double diffused metal oxide semiconductor (LDMOS) device, comprising: 
 a substrate of a first conductivity type;    a well region of a second conductivity type formed in the substrate, the well region having a super steep retrograde (SSR) well profile in which a doping concentration changes with depth so as to provide a lighter dopi9ng concentration in a surface region of the well region than in a region below the surface region of the well region;    a gate which partly overlies a portion of the substrate of the first conductivity type adjacent to the well region said portion including a channel for the LDMOS device, and partly overlies the well region;    one of a source region and a drain region in the well region, and the other of the source region and the drain region in said portion of the substrate.    
   
   
       2 . An LDMOS device as claimed in  claim 1 , wherein the well region contains a first element implanted in the substrate to form the well region of the second conductivity type, and a second element implanted in the well region to produce the SSR well profile within the well region.  
   
   
       3 . An LDMOS device as claimed in  claim 2 , wherein the second element is heavier than the first element.  
   
   
       4 . An LDMOS device as claimed in  claim 3 , wherein the first element is selected from the lighter Group VI elements and the second element is selected from the heavier Group VI elements.  
   
   
       5 . An LDMOS device as claimed in  claim 4 , wherein the first element is Phosphorus (P) and the second element is Antimony (Sb).  
   
   
       6 . An LDMOS device as claimed in  claim 1 , further comprising: 
 a second well region of the first conductivity type formed in the substrate adjacent the well region of the second conductivity type.    
   
   
       7 . An LDMOS device as claimed in  claim 1 , further comprising: 
 a field oxide insulating layer and an adjacent gate oxide layer formed on the surface of the substrate, the gate layer being formed so as to overlie the gate oxide layer and at least a portion of the field oxide insulating layer.    
   
   
       8 . An LDMOS device as claimed in  claim 1 , wherein the first conductivity type is P type and the second conductivity type is N type.  
   
   
       9 . An LDMOS device as claimed in  claim 8 , wherein the well region of the second conductivity type is an N-minus region.