Higher performance CMOS on (110) wafers

Abstract

A semiconductor (e.g., complementary metal oxide semiconductor (CMOS)) structure formed on a (110) substrate that has improved performance, in terms of mobility enhancement is provided. In accordance with the present invention, the inventive structure includes at least one of a single tensile stressed liner, a compressively stressed shallow trench isolation (STI) region, or a tensile stressed embedded well, which is used in conjunction with the (110) substrate to improve carrier mobility of both nFETs and pFETs. The present invention also relates to a method of providing such structures.

1 . A semiconductor structure comprising 
 a semiconductor substrate having a (110) surface; and    at least one nFETs and at least one pFET located on said semiconductor substrate, wherein said at least one nFETs and said at least one pFET both have a strained channel along a <100> channel direction.    
   
   
       2 . The semiconductor structure of  claim 1  wherein each of said strained channels is a result of including at least one of a single tensile stressed liner, a compressively stressed shallow trench isolation (STI) region, or a tensile stressed embedded well in source/drain areas.  
   
   
       3 . The semiconductor structure of  claim 2  wherein each of said strained channels is a result of said single tensile stressed liner.  
   
   
       4 . The semiconductor structure of  claim 2  wherein each of said strained channels is a result of said single tensile stressed liner and said compressively stressed STI region.  
   
   
       5 . The semiconductor structure of  claim 2  wherein each of said strained channels is a result of said compressively stressed STI region and said tensile stressed embedded well.  
   
   
       6 . The semiconductor structure of  claim 2  wherein each of said strained channels is a result of said single tensile stressed liner, said compressively stressed shallow trench isolation (STI) region, and said tensile stressed embedded well.  
   
   
       7 . The semiconductor structure of  claim 1  wherein said semiconductor substrate is a bulk semiconductor material or a semiconductor-on-insulator.  
   
   
       8 . The semiconductor structure of  claim 1  wherein said semiconductor substrate is relaxed or bi-axially strained.  
   
   
       9 . A semiconductor structure comprising: 
 a semiconductor substrate having a (110) surface; and    at least one nFETs and at least one pFET located on said semiconductor substrate, wherein said at least one nFET and said at least one pFET both have a strained channel along a <100> channel direction, said strained channel is a result of having a single tensile stressed liner covering said at least one nFETs and said at least one pFET.    
   
   
       10 . The semiconductor structure of  claim 9  further comprising a compressively stressed STI region between said at least one nFET and said at least one pFET.  
   
   
       11 . The semiconductor structure of  claim 9  further comprising a tensile stressed embedded well located within each source/drain region of said at least one nFET and said at least one pFET.  
   
   
       12 . The semiconductor structure of  claim 9  further comprising a compressively stressed STI region between said at least one nFET and said at least one pFET and a tensile stressed embedded well located within each source/drain region of said at least one nFETs and said at least one pFET.  
   
   
       13 . A semiconductor structure comprising: 
 a semiconductor substrate having a (110) surface; and    at least one nFETs and at least one pFET located on said semiconductor substrate, wherein said at least one nFETs and said at least one pFET both have a strained channel along a <100> channel direction, said strained channel is a result of having a single tensile stressed liner covering said at least one nFETs and said at least one pFET and a compressively stressed shallow trench isolation in said semiconductor substrate between said at least one nFET and said at least one pFET.    
   
   
       14 . The semiconductor structure of  claim 13  further comprising a tensile stressed embedded well located within each source/drain region of said at least one nFET and said at least one pFET.  
   
   
       15 . A method of forming a semiconductor structure comprising: 
 forming at least one nFET and at least one pFET located on a semiconductor substrate having a (110) surface, wherein said at least one nFETs and said at least one pFET both have a strained channel along a <100> channel direction.    
   
   
       16 . The method of  claim 15  wherein each of said strained channels is a result of including at least one of a single tensile stressed liner, a compressively stressed shallow trench isolation (STI) region, or a tensile stressed embedded well.  
   
   
       17 . The method of  claim 16  wherein each of said strained channels is a result of said single tensile stressed liner.  
   
   
       18 . The method of  claim 16  wherein each of said strained channels is a result of said single tensile stressed liner and said compressively stressed STI region.  
   
   
       19 . The method of  claim 16  wherein each of said strained channels is a result of said compressively stressed STI region and said tensile stressed embedded well.  
   
   
       20 . The method of  claim 16  wherein each of said strained channels is a result of said single tensile stressed liner, said compressively stressed shallow trench isolation (STI) region, and said tensile stressed embedded well.