Method of packing-based macro placement and semiconductor chip using the same

Abstract

A multi-packing tree (MPT) macro placer. The MPT macro placer comprises reading input files in a LEF/DEF format, creating a k-level binary multi-packing tree comprising k branch nodes each corresponding to one level and k+1 packing sub-trees each corresponding to one of the nodes and comprising a group of macros, optimizing the multi-packing tree according to a packing result thereof, and generating output files in a DEF format.

1 . A semiconductor chip, comprising:
 a first group of macros close packed toward a first direction of the semiconductor chip; and   a second group of macros close packed toward a second direction of the semiconductor chip.   
   
   
       2 . The semiconductor chip as claimed in  claim 1 , wherein the first or second group of macros comprises a macro cluster comprising a plurality of macros with the same height and width within the same group of design hierarchy. 
   
   
       3 . The semiconductor chip as claimed in  claim 1 , further comprising a placement blockage or pre-placed macro disposed in the first or second group of macros without overlap. 
   
   
       4 . A semiconductor chip, comprising:
 a first group of macros close packed toward a first edge of the semiconductor chip; and   a second group of macros close packed toward a second edge of the semiconductor chip.   
   
   
       5 . The semiconductor chip as claimed in  claim 4 , wherein the first or second group of macros comprises a macro cluster comprising a plurality of macros with the same height and width within the same group of design hierarchy. 
   
   
       6 . The semiconductor chip as claimed in  claim 4 , further comprising a placement blockage or pre-placed macro disposed in the first or second group of macros without overlap. 
   
   
       7 . A semiconductor chip, comprising:
 a first group of macros close packed toward a first corner of the semiconductor chip; and   a second group of macros close packed toward a second corner of the semiconductor chip.   
   
   
       8 . The semiconductor chip as claimed in  claim 7 , wherein the first or second group of macros comprises a macro cluster comprising a plurality of macros with the same height and width within the same group of design hierarchy. 
   
   
       9 . The semiconductor chip as claimed in  claim 7 , further comprising a placement blockage or pre-placed macro disposed in the first or second group of macros without overlap. 
   
   
       10 . The semiconductor chip as claimed in  claim 7 , wherein each of the first and second group of macros corresponds to a binary packing sub-tree comprising a corner macro at a root thereof. 
   
   
       11 . A method of macro placement, comprising:
 creating a k-level binary multi-packing tree; and   packing the macros of each packing sub-tree in a placement region;   wherein the k-level binary multi-packing tree comprises k branch nodes each corresponding to one level, and k+1 packing sub-trees each corresponding to one of the nodes and comprising a group of macros.   
   
   
       12 . The method of macro placement as claimed in  claim 11 , wherein the macros of each packing sub-tree are close packed toward a direction of the placement region and the direction corresponding to each packing sub-tree is different from others. 
   
   
       13 . The method of macro placement as claimed in  claim 11 , wherein the macros of each packing sub-tree are close packed toward an edge of the placement region and the edge corresponding to each packing sub-tree is different from others. 
   
   
       14 . The method of macro placement as claimed in  claim 11 , wherein the macros of each packing sub-tree are close packed toward a corner of the placement region and the corner corresponding to each packing sub-tree is different from others. 
   
   
       15 . A multi-packing tree (MPT) macro placer, comprising steps of:
 reading input files in a LEF/DEF format;   creating a k-level binary multi-packing tree comprising k branch nodes each corresponding to one level and k+1 packing sub-trees each corresponding to one of the nodes and comprising a group of macros;   optimizing the multi-packing tree according to a packing result thereof; and   generating output files in a DEF format.   
   
   
       16 . The MPT macro placer as claimed in  claim 15 , further comprising adjusting spacing between macros after packing of the macros. 
   
   
       17 . The MPT macro placer as claimed in  claim 15 , further comprising clustering the macros with the same height and width within the same group of design hierarchy after reading the input files in the LEF/DEF format and declustering the macros before generating the output files in the DEF format. 
   
   
       18 . The MPT macro placer as claimed in  claim 17 , wherein optimizing the multi-packing tree comprises iteration of a simulated annealing loop comprising perturbing the multi-packing tree, packing the macros in the multi-packing tree, evaluating macro placement of packing, and accepting or rejecting the macro placement. 
   
   
       19 . The MPT macro placer as claimed in  claim 18 , wherein the simulated annealing loop further comprises fixing structure of the multi-packing tree according to within given macro placement constraints. 
   
   
       20 . The MPT macro placer as claimed in  claim 18 , wherein the iteration of the simulated annealing loop ends when a packing solution is acceptable or no better packing solution can be found. 
   
   
       21 . The MPT macro placer as claimed in  claim 18 , wherein perturbing the multi-packing tree comprises rotating a macro block or a macro cluster, resizing a macro cluster, moving one of the nodes in one of the packing sub-trees to another place, swapping two nodes within the same or different packing sub-trees, swapping two packing sub-trees or a combination thereof. 
   
   
       22 . A mixed-size placement design method, comprising:
 reading initial input files in a LEF/DEF format;   performing preliminary macro placement with a conventional macro placer;   performing detailed macro placement with the MPT macro placer as claimed in  claim 15 ; and   generating final output files in a DEF format.   
   
   
       23 . The mixed-size placement design method as claimed in  claim 22 , further comprising performing standard cell placement before generating final output files in a DEF format.