Nonvolatile semiconductor memory device having excellent charge retention and manufacturing process of the same

Abstract

There has been a problem in conventional Si-type floating-gate type nonvolatile semiconductor memory devices that the charge retention characteristic is low due to insufficiently large electron affinity of Si, therefore improvement of the memory performances, such as scaling down of a memory cell and increasing operation speed, have been difficult to be achieved due to the essential problem. In order to solve the above problem, in the nonvolatile semiconductor memory device of the present invention, a material having large work function or large electron affinity or a material having a work function close to that of semiconductor substrate or of a control gate, is employed for a floating gate retaining charges. Further, an amorphous material having small electron affinity for an insulating matrix is used. Further, at a time of deposition of charge retention layer, the supply ratio of the nano-particle material and the insulating matrix material, such as the mixture ratio of materials of both phases in a target in a sputtering method, is adjusted. By these methods, the charge retention characteristic of the floating-gate type nonvolatile semiconductor memory device can be improved, and the above-mentioned problem of the nonvolatile semiconductor memory device can be solved.

1 - 6 . (canceled)  
   
   
       7 . A process for manufacturing a nonvolatile semiconductor memory device that has a charge retention layer including nano-particles dispersed two-dimensionally or three-dimensionally in the insulating matrix, comprising: 
 forming the charge retention layer in a self-organizing manner by physical vapor deposition of each material to constitute the nano-particles and the insulating matrix.    
   
   
       8 . The process for manufacturing the nonvolatile semiconductor memory device according to  claim 7 , wherein the physical vapor deposition is performed by a sputtering method.  
   
   
       9 - 14 . (canceled)  
   
   
       15 . A process for manufacturing a nonvolatile semiconductor memory device that has a charge retention layer including nano-particles dispersed two-dimensionally or three-dimensionally in an insulating matrix, comprising: 
 forming a source region and a drain region on a surface of a semiconductor substrate;    forming a channel-forming region so as to connect the source region and the drain region or so as to be sandwiched between the source region and the drain region;    forming a tunnel insulating film in contact with the channel-forming region;    forming the charge retention layer adjacent to the tunnel insulating film in a self-organizing manner by physical vapor deposition of each material of the nano-particles and the insulating matrix;    forming a gate insulating film adjacent to the charge retention layer; and    forming a control gate adjacent to the gate insulating film.    
   
   
       16 . The process for manufacturing the nonvolatile semiconductor memory device according to  claim 15 , wherein the physical vapor deposition is performed by a sputtering method.  
   
   
       17 . The method of  claim 15 , wherein the forming the charge retention layer comprises: 
 forming at least one conductive nano-particle which is made of at least one single-element substance or chemical compound that functions as a floating gate and has a particle size of at most 5 nm.    
   
   
       18 . The method of  claim 15 , wherein the forming the charge retention layer comprises: 
 forming a plurality of conductive nano-particles of the same type independently dispersed with a density of from 10 +12  to 10 +14  particles per square centimeter in the charge retention layer.    
   
   
       19 . The method of  claim 15 , wherein the forming the charge retention layer comprises: 
 forming an amorphous insulating matrix having an electron affinity of at most 1.0 eV.    
   
   
       20 . The method of  claim 15 , wherein the forming the charge retention layer comprises: 
 forming in the charge retention layer conductive nano-particles having a work function of at least 4.2 eV.    
   
   
       21 . The method of  claim 15 , wherein the forming the charge retention layer comprises: 
 forming the charge retention layer with materials having a difference between a work function of the nano-particles and a work function of the semiconductor substrate of at most 0.5 eV.    
   
   
       22 . The method of  claim 15 , wherein the forming the charge retention layer comprises: 
 forming the charge retention layer with materials having a difference between a work function of the nano-particles and a work function of the control gate of at most 0.5 eV.    
   
   
       23 . The method of  claim 15 , wherein the forming the charge retention layer comprises: 
 forming the charge retention layer such that the distance between surfaces of the nano-particles adjacent to each other is from 1 to 5 nm.    
   
   
       24 . The method of  claim 15 , wherein the forming the charge retention layer comprises: 
 forming the charge retention layer from at least one chemical compound selected from the group consisting of an oxide, a carbide, a nitride, a boride, a silicide, and a fluoride.    
   
   
       25 . The method of  claim 15 , wherein the forming the charge retention layer comprises: 
 forming the charge retention layer such that the nano-particles included the charge retention layer are dispersed two-dimensionally or three-dimensionally in the insulating matrix.    
   
   
       26 . The method of  claim 15 , wherein the forming the charge retention layer comprises: 
 forming at least one semiconductive or insulating nano-particle in the charge retention layer.    
   
   
       27 . The method of  claim 26 , wherein the forming at least one semiconductive or insulating nano-particle in the charge retention layer comprises: 
 forming the semiconductive or insulating nano-particle having a particle size of at most 5 nm.    
   
   
       28 . The method of  claim 26 , wherein the forming at least one semiconductive or insulating nano-particle in the charge retention layer comprises: 
 forming a plurality of semiconductive or insulating nano-particles of the same type independently dispersed with a density of from 10 +12  to 10 +14  particles per square centimeter in the charge retention layer.    
   
   
       29 . The method of  claim 26 , wherein the forming the charge retention layer comprises comprises: 
 forming an amorphous insulating matrix having an electron affinity of at most 1.0 eV.    
   
   
       30 . The method of  claim 26 , wherein the forming the charge retention layer comprises: 
 forming in the charge retention layer nano-particles having an electron affinity of at least 4.2 eV.    
   
   
       31 . The method of  claim 26 , wherein the forming the charge retention layer comprises: 
 forming the charge retention layer with materials having a difference between a work function of the nano-particles and a work function of the semiconductor substrate of at most 0.5 eV.    
   
   
       32 . The method of  claim 26 , wherein the forming the charge retention layer comprises: 
 forming the charge retention layer with materials having a difference between a work function of the nano-particles and a work function of the control gate of at most 0.5 eV.    
   
   
       33 . The method of  claim 26 , wherein the forming the charge retention layer comprises: 
 forming the charge retention layer such that the distance between surfaces of the nano-particles adjacent to each other is from 1 to 5 nm.    
   
   
       34 . The method of  claim 26 , wherein the forming the charge retention layer comprises: 
 forming the charge retention layer from at least one chemical compound selected from the group consisting of an oxide, a carbide, a nitride, a boride, a silicide, and a fluoride.    
   
   
       35 . The method of  claim 26 , wherein the forming the charge retention layer comprises: 
 forming the charge retention layer such that the nano-particles included the charge retention layer are dispersed two-dimensionally or three-dimensionally in the insulating matrix.