Method of manufacturing split gate flash memory

Abstract

A split gate flash memory is provided. Trenches are formed in the substrate to define active layers. The device isolation layers are formed in the trenches. The surface of the device isolation layers is lower than the surface of the active layers. The stacked gate structures each including a tunneling dielectric layer, a floating gate and a cap layer are formed on the active layers. The inter-gate dielectric layers are formed on the sidewalls of the stacked gate structures. The select gates are formed on one side of the stacked gate structure and across the active layer. The select gate dielectric layers are formed between the select gates and the active layers. The source regions are formed in the active layers on the other side of the stacked gate structures. The drain regions are formed in the active layers on one side of the select gates.

1 . A method of manufacturing a split gate flash memory, comprising: 
 providing a substrate;    forming an active layer on the substrate, wherein the active layer protrudes from the surface of the substrate;    forming a plurality of device isolation layers on the sides of the active layer, wherein the surface of the device isolation layers is lower than the surface of the active layer;    forming a stacked gate structure on the substrate, wherein the stacked gate structure comprises at least a floating gate that formed across the active layer;    forming a source region in the active layer on a first side of the stacked gate structure;    forming a select gate on the sidewall of a second side of the stacked gate structure and on the active layer; and    forming a drain region in the active layer on one side of the select gate.    
   
   
       2 . The method of  claim 1 , wherein the stack gate structure comprises: 
 a tunneling dielectric layer formed between the floating gate and the active layer; and    a cap layer formed on the floating gate.    
   
   
       3 . The method of  claim 2 , wherein the step of forming the stacked gate structure on the substrate comprises: 
 forming a dielectric layer, a first conductive layer and a mask layer sequentially over the substrate;    patterning the mask layer to form an opening that exposes a portion of the first conductive layer;    forming a cap layer on the exposed first conductive layer;    removing the mask layer; and    etching the first conductive layer and the dielectric layer using the cap layer as a mask to form the stacked gate structure.    
   
   
       4 . The method of  claim 1 , wherein the step of forming the select gate on the sidewall on the second side of the stacked gate structure and on the first active layer comprises: 
 forming a second conductive layer over the substrate; and    patterning the second conductive layer to form the select gate on the sidewall on the second side of the stacked gate structure and on the first active layer.    
   
   
       5 . The method of  claim 1 , wherein after forming the stacked gate structure on the substrate, further comprises: 
 forming an inter-gate dielectric layer on the sidewalls of the stacked gate structure; and    forming a select gate dielectric layer on the active layer on the second side of the stacked gate structure.    
   
   
       6 . The method of  claim 5 , wherein the step of forming the inter-gate dielectric layer on the sidewalls of the stacked gate structure comprises performing a thermal oxidation process.  
   
   
       7 . The method of  claim 1 , wherein the step of forming the active layers on the substrate comprises forming a plurality of trenches in the substrate.  
   
   
       8 . A method of manufacturing a split gate flash memory, comprising: 
 providing a substrate;    forming a plurality of first active layers and a plurality of second active layers on the substrate, wherein the first active layers are aligned in a first direction parallel to one another and the second active layers are aligned in a second direction parallel to one another such that the first direction crosses the second direction, and the first active layers and the second active layers protrude from the surface of the substrate;    forming a plurality of device isolation layers on the sides of the first active layers and the second active layers, wherein the surface of the device isolation layers is lower than the surface of the first active layers and the second active layers;    forming a plurality of stacked gate structures on the substrate, wherein the stacked gate structures are aligned to form an array and each stacked gate structure comprises at least a floating gate is formed across the first active layer;    forming a plurality of source regions in the first active layer and the second active layer between two adjacent stacked gate structures, wherein the source regions in the second direction are serially connected together through the respective second active layers;    forming a plurality of select gates on one sidewall of the stacked gate structures and on the first active layers, wherein the select gates in the second direction are connected to one another; and    forming a plurality of drain regions in the respective first active layers on a reciprocal side of the select gates and the source regions.    
   
   
       9 . The method of  claim 8 , wherein the stacked gate structure further comprises: 
 a tunneling dielectric layer formed between the floating gate and the active layer, and    a cap layer formed on the floating gate.    
   
   
       10 . The method of  claim 9 , wherein the step of forming the stacked gate structures on the substrate comprises: 
 forming a dielectric layer, a first conductive layer and a mask layer sequentially over the substrate;    patterning the mask layer to form a plurality of openings that exposes a portion of the first conductive layer;    forming a cap layer on the exposed first conductive layer;    removing the mask layer;    etching the first conductive layer and the dielectric layer using the cap layer as a mask to form the stacked gate structures.    
   
   
       11 . The method of  claim 8 , wherein the step of forming the select gates on one sidewall of the stacked gate structures and on the first active layers comprises: 
 forming a second conductive layer over the substrate; and    patterning the second conductive layer to form the select gates on the sidewalls of the stacked gate structures and on the first active layers.    
   
   
       12 . The method of  claim 8 , wherein after forming the stacked gate structures on the substrate, further comprises: 
 forming an inter-gate dielectric layer on the respective sidewalls of the stacked gate structures; and    forming a select gate dielectric layer on one side of the stacked gate structures and on the first active layers.    
   
   
       13 . The method of  claim 12 , wherein the step of forming the inter-gate dielectric layer on the sidewalls of the stacked gate structure comprises performing a thermal oxidation process.  
   
   
       14 . The method of  claim 8 , wherein the step of forming the first active layers and the second active layers on the substrate comprises forming a plurality of trenches in the substrate.