High performance CMOS circuits, and methods for fabricating the same

Abstract

The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits that each contains at least a first and a second gate stacks. The first gate stack is located over a first device region (e.g., an n-FET device region) in a semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer, a metallic gate conductor, and a silicon-containing gate conductor. The second gate stack is located over a second device region (e.g., a p-FET device region) in the semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer and a silicon-containing gate conductor. The first and second gate stacks can be formed over the semiconductor substrate in an integrated manner by various methods of the present invention.

1 . A semiconductor device comprising: 
 a semiconductor substrate containing at least first and second device regions adjacent to each other;    a first gate stack located over the first device region, wherein said first gate stack comprises at least, from bottom to top, a gate dielectric layer comprising a dielectric material having a dielectric constant (k) equal to or greater than that of silicon dioxide, a metallic gate conductor, and a silicon-containing gate conductor; and    a second gate stack located over the second device region, wherein said second gate stack comprises at least, from bottom to top, a gate dielectric layer and a silicon-containing gate conductor.    
   
   
       2 . The semiconductor device of  claim 1 , wherein the gate dielectric layer of the first gate stack comprises a hafnium-based dielectric material selected from the group consisting of hafnium oxide, hafnium silicate, hafnium semiconductor oxynitride, a mixture of hafnium oxide and zirconium oxide, and multilayers thereof.  
   
   
       3 . The semiconductor device of  claim 1 , wherein the metallic gate conductor of the first gate stack comprises a metal nitride or a metal silicon nitride that contains a Group IVB or VB metal.  
   
   
       4 . The semiconductor device of  claim 3 , wherein the metallic gate conductor of the first gate stack comprises TiN, TaN, a ternary alloy of Ti-AE-N, a ternary alloy of Ta-AE-N, a ternary alloy of Ti-RE-N, a ternary alloy of Ta-RE-N, or a stack comprising mixtures thereof.  
   
   
       5 . The semiconductor device of  claim 1 , wherein the silicon-containing gate conductor of the first gate stack and the silicon-containing gate conductor of the second gate stack both comprise polycrystalline silicon.  
   
   
       6 . The semiconductor device of  claim 1 , wherein the first gate stack further comprises an interfacial layer located beneath the gate dielectric layer and an additional silicon-containing gate conductor located above the silicon-containing gate conductor, and wherein the second gate stack further comprises an additional silicon-containing gate conductor located above the silicon-containing gate conductor.  
   
   
       7 . The semiconductor device of  claim 1 , wherein the first gate dielectric stack further comprises a conductive oxygen barrier layer located above the metallic gate conductor and beneath the silicon-containing gate conductor.  
   
   
       8 . The semiconductor device of  claim 7 , wherein the conductive oxygen barrier layer comprises tantalum silicon nitride or hafnium silicon nitride.  
   
   
       9 . The semiconductor device of  claim 1 , wherein the first gate dielectric stack further comprises an interfacial layer located beneath the gate dielectric layer, and a rare earth metal-containing or an alkaline earth metal-containing layer located above, or within, the gate dielectric layer and beneath the metallic gate conductor.  
   
   
       10 . The semiconductor device of  claim 9 , wherein the first gate dielectric stack comprises a rare earth metal-containing layer.  
   
   
       11 . The semiconductor device of  claim 10 , wherein the rare earth metal-containing layer comprises an oxide or nitride of at least one rare earth metal.  
   
   
       12 . The semiconductor device of  claim 9 , wherein the first gate dielectric stack comprises a alkaline earth metal-containing layer.  
   
   
       13 . The semiconductor device of  claim 12 , wherein the alkaline earth metal-containing layer comprises a compound having the formula M x A y , wherein M is at least one alkaline earth metal, and wherein A is one of O, S, or a halide, and x is 1 or 2 and y is 1, 2 or 3.  
   
   
       14 . A method for forming the semiconductor device of  claim 1 , comprising: 
 forming a first gate dielectric layer and a silicon-containing gate conductor selectively over the second device region of the semiconductor substrate;    forming a protective capping layer selectively over the second device region;    forming a second gate dielectric layer and a metallic gate conductor selectively over the first device region of the semiconductor substrate, wherein the second gate dielectric layer comprises a dielectric material having a dielectric constant (k) greater than or equal to that of silicon dioxide;    removing the protective capping layer from the second device region;    depositing a silicon-containing layer over both the first and second device regions; and    patterning the silicon-containing layer, the metallic gate conductor, the second gate dielectric layer, the silicon-containing gate conductor, and the first gate dielectric layer to form first and second gate stacks.    
   
   
       15 . A method for forming the semiconductor device of  claim 1 , comprising: 
 forming a first gate dielectric layer, a metallic gate conductor and a silicon-containing gate conductor selectively over the first device region of the semiconductor substrate, wherein the first gate dielectric layer comprises a dielectric material having a dielectric constant (k) greater than or equal to that of silicon dioxide;    forming a second gate dielectric layer over both the first and second device regions;    depositing a silicon-containing layer over both the first and second device regions;    planarizing the silicon-containing layer, the second gate dielectric layer and the silicon-containing gate conductor, so as to remove portions of the silicon-containing layer and the second gate dielectric layer from the first device region and to expose an upper surface of the silicon-containing gate conductor in the first device region, and wherein the exposed silicon-containing gate conductor in the first device region is substantially coplanar with the un-removed portion of the silicon-containing layer in the second device region; and    patterning the exposed silicon-containing gate conductor, the metallic gate conductor, the first gate dielectric layer and the un-removed portions of the silicon-containing layer and the second gate dielectric layer to form first and second gate stacks.    
   
   
       16 . A method for forming the semiconductor device of  claim 1 , comprising: 
 forming a first dielectric layer, a metallic gate conductor and a silicon-containing gate conductor selectively over the first device region of the semiconductor substrate, wherein the first gate dielectric layer comprises a dielectric material having a dielectric constant (k) greater than or equal to that of silicon dioxide;    forming a second gate dielectric layer over both the first and second device regions;    depositing a silicon-containing layer over both the first and second device regions;    selectively etching the silicon-containing layer to remove a portion of the silicon-containing layer from the first device region;    selectively etching the second gate dielectric layer to remove a portion of the second gate dielectric layer from the first device region, thereby exposing an upper surface of the silicon-containing gate conductor; and    patterning the exposed silicon-containing gate conductor, the metallic gate conductor, the first gate dielectric layer and un-removed portions of the silicon-containing layer and the second gate dielectric layer to form first and second gate stacks.    
   
   
       17 . A method for forming the semiconductor device of  claim 6 , comprising: 
 forming a first gate dielectric layer and a silicon-containing gate conductor selectively over the second device region of the semiconductor substrate;    forming an interfacial layer, a second dielectric layer, a metallic layer, and a silicon-containing layer over both the first and second device regions;    selectively remove the interfacial layer, the second dielectric layer, the metallic layer, and the silicon-containing layer from the second device region, thereby exposing an upper surface of the silicon-containing gate conductor in the second device region;    forming an additional silicon-containing layer over both the first and second device regions; and    patterning the additional silicon-containing layer, the silicon-containing layer, the metallic layer, the second dielectric layer, the interfacial layer, the silicon-containing gate conductor and the first gate dielectric layer to form first and second gate stacks.    
   
   
       18 . A method for forming the semiconductor device of  claim 7 , comprising: 
 forming a first dielectric layer, a metallic gate conductor and a conductive oxygen diffusion barrier layer selectively over the first device region of the semiconductor substrate;    oxidizing an exposed upper surface of the semiconductor substrate in the second device region to form a second gate dielectric layer, wherein the conductive oxygen diffusion barrier layer protects the first device region from oxidation;    depositing a silicon-containing layer over both the first and second device regions; and    patterning the silicon-containing layer, the conductive oxygen diffusion barrier layer, the metallic gate conductor, the first gate dielectric layer, and the second gate dielectric layer to form first and second gate stacks.    
   
   
       19 . A method for forming the semiconductor device of  claim 1 , comprising: 
 forming a first dielectric layer, a metallic gate conductor and an insulating oxygen diffusion barrier layer selectively over the first device region of the semiconductor substrate;    oxidizing an exposed upper surface of the semiconductor substrate in the second device region to form a second gate dielectric layer, wherein the insulating oxygen diffusion barrier layer protects the first device region from oxidation;    removing the insulating oxygen diffusion barrier layer from the first device region to expose an upper surface of the metallic gate conductor;    depositing a silicon-containing layer over both the first and second device regions; and    patterning the silicon-containing layer, the metallic gate conductor, the first gate dielectric layer, and the second gate dielectric layer to form first and second gate stacks.    
   
   
       20 . A method for forming the semiconductor device of  claim 9 , wherein the gate dielectric layer of the first gate stack is a high k gate dielectric layer that comprises hafnium oxide, comprising: 
 forming an interfacial layer and a hafnium layer selectively over the first device region of the semiconductor substrate;    oxidizing the hafnium layer to form a high k gate dielectric layer that comprises hafnium oxide in the first device region, wherein an upper surface of the semiconductor substrate in the second device region is concurrently oxidized to form a gate dielectric layer in the second device region;    forming a rare earth metal-containing or an alkaline-earth metal-containing layer selectively over the first device region;    depositing a metallic layer over both the first and second device regions;    selectively removes the metallic layer from the second device region, thereby exposing an upper surface of the gate dielectric layer in the second device region;    depositing a silicon-containing layer over both the first and second device regions; and    patterning the silicon-containing layer, the metallic layer, the rare earth metal-containing or alkaline earth metal-containing layer, the high k gate dielectric layer, the interfacial layer, and the gate dielectric layer to form first and second gate stacks.