Dynamic random access memory cell layout and fabrication method thereof

Abstract

A dynamic random access memory (DRAM) cell layout for arranging deep trenches and active areas and a fabrication method thereof. An active area comprises two vertical transistors, a common bitline contact and two deep trenches. The first vertical transistor is formed on a region where the first deep trench is partially overlapped with the first gate conductive line. The second vertical transistor is formed on a region where the second deep trench is partially overlapped with the second gate conductive line.

1 - 18 . (canceled)  
   
   
       19 . A transistor, comprising: 
 a source/drain region;    a buried strap out-diffusion region adjacent to one sidewall of a deep trench; and    a bended gate structure having a bended gate and a bended gate insulating layer, wherein the bended gate structure comprises a first portion extending along a first direction and a second portion extending along a second direction intersecting with the first direction, wherein the first portion of the bended gate is adjacent to the source/drain region and the second portion of the bended gate is adjacent to the buried strap out-diffusion region, and on an overlapping region between the deep trench and the bended gate structure, the sidewall profile of the deep trench comprises at least three edges.    
   
   
       20 . The transistor as claimed in  claim 19 , wherein the deep trench is a trench of a deep trench capacitor.  
   
   
       21 . The transistor as claimed in  claim 19 , wherein the bended gate is adjacent to a shallow trench isolation.  
   
   
       22 . The transistor as claimed in  claim 19 , further comprising a bit line contact electrically contacting the source/drain region.  
   
   
       23 . The transistor as claimed in  claim 21 , wherein the bit line contact is separated from the bit line contact by a spacer on a sidewall of the bended gate.  
   
   
       24 . The transistor as claimed in  claim 19 , wherein the bended gate is L shaped in a cross section view.  
   
   
       25 . The transistor as claimed in  claim 19 , wherein the bended gate insulating layer is L shaped in a cross section view.  
   
   
       26 . The transistor as claimed in  claim 19 , wherein the first direction and the second direction are perpendicular.  
   
   
       27 . The transistor as claimed in  claim 19 , wherein the source/drain region is disposed in a substrate.  
   
   
       28 . The transistor as claimed in  claim 27 , wherein the first direction is parallel to the substrate surface.  
   
   
       29 . The transistor as claimed in  claim 19 , wherein the second direction is parallel to a sidewall of the trench.  
   
   
       30 . A memory device, comprising a deep trench capacitor and a transistor controlling the deep trench capacitor, wherein the transistor is as claimed in  claim 19 .  
   
   
       31 . The transistor as claimed in  claim 19 , wherein on the overlapping region between the deep trench and bended gate structure, the sidewall profile of the deep trench comprises at least five edges.  
   
   
       32 . A memory device, comprising: 
 a source/drain region;    a buried strap out-diffusion region adjacent to one sidewall of a deep trench; and    a bended gate structure having a bended gate and a bended gate insulating layer, wherein the bended gate structure comprises a first portion extending along a first direction and a second portion extending along a second direction intersecting with the first direction, wherein the first portion of the bended gate is adjacent to the source/drain region and the second portion of the bended gate is adjacent to the buried strap out-diffusion region, and on an overlapping region between the deep trench and the bended gate structure, the sidewall profile of the deep trench is  -shaped.