Method of forming copper interconnections in semiconductor devices

Abstract

A method of forming a copper interconnection including at least one of: Forming an interlayer dielectric layer over a silicon substrate. Forming a plurality of via holes and trench patterns in an interlayer dielectric layer; forming a photoresist pattern over an interlayer dielectric layer between a plurality of via hole and trench patterns. Performing an electroplating process on a silicon substrate so that copper may be filled in a plurality of via holes and trench patterns. Planarizing a copper layer so that a photoresist pattern is removed.

1 . A method comprising:
 forming a dielectric layer over a semiconductor substrate;   forming at least one of a via hole and a trench pattern in the dielectric layer;   forming a photoresist pattern over the dielectric layer in areas wherein said at least one of a via hole and a trench pattern are not formed; and   electroplating metal over said photoresist pattern.   
   
   
       2 . The method of  claim 1 , comprising planarizing electroplated metal. 
   
   
       3 . The method of  claim 2 , wherein said planarizing comprises removing the photoresist pattern. 
   
   
       4 . The method of  claim 1 , wherein the method forms a copper interconnection. 
   
   
       5 . The method of  claim 1 , wherein the dielectric layer is an interlayer dielectric layer. 
   
   
       6 . The method of  claim 1 , wherein said electroplating metal is electroplating copper. 
   
   
       7 . The method of  claim 1 , wherein said electroplating metal comprises filling said at least one of a via hole and a trench pattern with metal. 
   
   
       8 . The method of  claim 1 , wherein the dielectric layer comprises a low-k dielectric material. 
   
   
       9 . The method of  claim 1 , wherein said electroplating metal comprises electroplating metal to have a thickness less than approximately 7000 Å. 
   
   
       10 . The method of  claim 9 , wherein said electroplating metal comprises electroplating metal to have a thickness less than approximately 5000 Å. 
   
   
       11 . The method of  claim 1 , wherein said at least one of a via hole and a trench pattern include concentration and non-concentration areas. 
   
   
       12 . An apparatus comprising:
 a dielectric layer formed over a semiconductor substrate;   at least one of a via hole and a trench pattern formed in the dielectric layer; and   metal electroplated over said photoresist pattern, wherein the metal is electroplated by forming a photoresist pattern formed over the dielectric layer in areas wherein said at least one of a via hole and a trench pattern are not formed.   
   
   
       13 . The apparatus of  claim 12 , wherein the metal is planarized. 
   
   
       14 . The apparatus of  claim 13 , wherein photoresist pattern is removed when the metal is planarized. 
   
   
       15 . The apparatus of  claim 12 , wherein the dielectric layer is an interlayer dielectric layer. 
   
   
       16 . The apparatus of  claim 12 , wherein said metal is copper. 
   
   
       17 . The apparatus of  claim 12 , wherein the dielectric layer comprises a low-k dielectric material. 
   
   
       18 . The apparatus of  claim 12 , wherein the metal is electroplated to have a thickness less than approximately 7000 Å. 
   
   
       19 . The apparatus of  claim 18 , wherein the metal is electroplated to have a thickness less than approximately 5000 Å. 
   
   
       20 . The apparatus of  claim 12 , wherein said at least one of a via hole and a trench pattern include concentration and non-concentration areas.