US2007151090A1PendingUtilityA1

Ceramic substrate

Assignee: EPCOS AG A GERMAN CORPPriority: Sep 14, 2001Filed: Dec 1, 2006Published: Jul 5, 2007
Est. expirySep 14, 2021(expired)· nominal 20-yr term from priority
H05K 3/4629C04B 2237/346C04B 2237/56C04B 2237/341Y10T29/49885C04B 2237/34C04B 2237/343H05K 3/4688C04B 2237/702C04B 2237/348C04B 35/6303C04B 2235/36C04B 2235/3205C04B 35/48C04B 2237/562C04B 2237/365B32B 2310/0843H05K 1/0306C04B 35/457C04B 35/10B32B 18/00C04B 37/001B32B 2315/02H10W 90/724H10W 99/00H10W 70/05
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Claims

Abstract

A ceramic substrate includes a stack of layers that contain a ceramic material and that are sintered together. One layer, such as a top layer in the stack, has a higher proportion of a sintering agent than an adjacent layer. A metal paste may be applied to a top layer of the stack.

Claims

exact text as granted — not AI-modified
1 - 16 . (canceled)  
   
   
       17 . A ceramic substrate comprising: 
 a stack of layers that contain a ceramic material and that are sintered together, wherein a first layer has a higher proportion of a sintering agent than an adjacent second layer.    
   
   
       18 . The ceramic substrate according to  claim 17 , wherein the higher proportion of sintering agent is between 5 and 30 percent by weight inclusive.  
   
   
       19 . The ceramic substrate according to  claim 17 , wherein a top layer of the stack of layers contains a higher proportion of sintering agent than the adjacent second layer.  
   
   
       20 . The ceramic substrate according to  claim 17 , further comprising: 
 a reaction layer between the first layer with the increased proportion of sintering agent of the adjacent second layer;    wherein ceramic material from the adjacent second layer has a thickness of 10 μm to 50 μm.    
   
   
       21 . The ceramic substrate according to  claim 19 , further comprising metal paste enameled onto the top layer.  
   
   
       22 . The ceramic substrate according to  claim 17 , further comprising conducting paths between at least two layers of the stack.  
   
   
       23 . The ceramic substrate according to  claim 22 , wherein at least one of the two layers contains an electrically conducting perforation that interconnects at least two connecting paths of different sides of the layer.  
   
   
       24 . The ceramic substrate according to  claim 20 , further comprising: 
 a first component attached to a surface of the ceramic substrate via wire bonding; and    a second component attached to a surface of the ceramic substrate via flip-chip mounting.    
   
   
       25 . The ceramic substrate according to  claim 24 , wherein at least one of the first component and the second component comprises a microwave filter.  
   
   
       26 . The ceramic substrate according to  claim 20 , further comprising: 
 wiring planes arranged among layers in the stack of layers, at least one of the wiring planes being at a boundary between two layers in the stack of layers.    
   
   
       27 . The ceramic substrate according to  claim 26 , wherein at least some of the layers in the stack of layers include holes that contain conductive material, the conductive material contacting the wiring planes to form conductive paths through the ceramic substrate.  
   
   
       28 . The ceramic substrate according to  claim 20 , further comprising: 
 electrically conductive areas between layers in the stack of layers, the electrically conductive layers being interconnected to form comb-like structures.    
   
   
       29 . The ceramic substrate according to  claim 20 , further comprising: 
 a spiral-shaped conducting path among the layers in the stack of layers.    
   
   
       30 . The ceramic substrate according to  claim 20 , further comprising: 
 plural spiral-shaped conducting paths among the layers in the stack of layers.    
   
   
       31 . The ceramic substrate according to  claim 30 , wherein the plural spiral-shaped conducting paths are aligned so as to from coils.  
   
   
       32 . The ceramic substrate according to  claim 17 , wherein the stack of layers comprises layers that are curved.  
   
   
       33 . The ceramic substrate according to  claim 17 , wherein at least two layers in an upper region of the stack of layers have a dielectric constant of 20.  
   
   
       34 . The ceramic substrate according to  claim 17 , further comprising: 
 a passive electrical component integrated into the ceramic substrate.    
   
   
       35 . The ceramic substrate according to  claim 34 , wherein the passive electrical component comprises a capacitor.

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