Semiconductor device and method for regional stress control
Abstract
Mechanical stress control may be achieved using materials having selected elastic moduli. These materials may be selectively formed by implantation, may be provided as a plurality of buried layers interposed between the substrate and the active area, and may be formed by replacing selected portions of one or more buried layers. Any one or more of these methods may be used in combination. Mechanical stress control may be useful in the channel region of a semiconductor device to maximize its performance. In addition, these same techniques and structures may be used for other purposes besides mechanical stress control.
Claims
exact text as granted — not AI-modified1 . A semiconductor device comprising:
a substrate; a dielectric layer overlying the substrate and in contact with the substrate, the dielectric layer comprising a first region having a first elastic modulus and a second region having a second elastic modulus that differs from the first elastic modulus; a semiconductor layer overlying and in contact with the dielectric layer; and an active device having a portion that is formed within the semiconductor layer and overlying the first region of the dielectric layer, wherein the first elastic modulus has a predetermined value to optimize stress in an element of the active device.
2 . The device of claim 1 further comprising:
a second active device having a portion that is formed within the semiconductor layer and overlying the second region of the dielectric layer, the second elastic modulus of the dielectric layer being selected to optimize stress in a portion of the second active device.
3 . The device of claim 2 wherein the active device is a first transistor and the second active device is a second transistor, the element of the active device comprising a channel of the first transistor and the portion of the second active device comprising a channel of the second transistor.
4 . The device of claim 2 wherein the active device is a P-channel transistor and the second active device is an N-channel transistor, the first elastic modulus of the first region of the dielectric layer having the predetermined value to either increase compressive stress or decrease tensile stress in a channel of the P-channel transistor, and the second elastic modulus of the second region of the dielectric layer being selected to either reduce compressive stress or increase tensile stress in a channel of the N-channel transistor.
5 . The device of claim 1 wherein the dielectric layer is a buried oxide layer comprising a third region having a third elastic modulus that is substantially equal to an unmodified modulus of the buried oxide layer, the first elastic modulus, second elastic modulus and third elastic modulus having different values.
6 . The device of claim 1 wherein the first region of the dielectric layer comprises a predetermined amount of at least one of boron, phosphorous or nitrogen or a combination of boron and phosphorous to create the first elastic modulus of the first region.
7 . The device of claim 1 wherein the second region of the dielectric layer comprises a predetermined amount of at least one of boron, phosphorous or nitrogen or a combination of boron and phosphorous to create the second elastic modulus of the second region.
8 - 25 . (canceled)
26 . A method for forming a semiconductor device, comprising:
forming a buried oxide layer overlying a substrate; forming a semiconductor layer overlying the buried oxide layer; implanting at least a portion of the buried oxide layer with an implant species, the implant species comprising at least one of a group consisting of nitrogen and carbon; and forming the semiconductor device overlying the at least the portion of the buried oxide layer.
27 . A method as in claim 26 , wherein the implant species comprises a concentration in a range of 1E19 to 5E22 atoms per cubic centimeter to modify an elastic modulus of the at least the portion of the buried oxide layer.Join the waitlist — get patent alerts
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