Calibration of oscillator devices

Abstract

A clock device having a resonating device such as a crystal of SAW supplying a controllable oscillator such as a digitally controlled oscillator is calibrated by supplying a calibration clock. A phase-locked loop is utilized to generate one or more correction factors causing the PLL to lock to the calibration clock. The one or more correction factors are then stored in non-volatile memory.

1 . A method to configure a device to generate an output signal having a particular frequency, the method comprising: 
 receiving a calibration clock signal over an input/output terminal of the device;    generating at least one control value in a calibration control loop of the device that includes a phase detector and a digitally controlled oscillator (DCO), to cause an output signal of the DCO to lock to a multiple of the calibration clock signal, thereby causing the device to generate the output signal having the particular frequency; and    storing a value corresponding to the at least one control value in a non-volatile memory in the integrated circuit.    
   
   
       2 . The method as recited in  claim 1  wherein the calibration control loop is a phase-locked loop.  
   
   
       3 . The method as recited in  claim 1  further comprising: 
 supplying another calibration clock signal to the device having a different frequency than the calibration clock signal;    generating at least one additional control value in the calibration control loop to cause the output signal of the DCO to lock to a multiple of the other calibration clock signal; and    storing another value corresponding to the at least one additional control value in the non-volatile memory.    
   
   
       4 . The method as recited in  claim 1  further comprising storing a history of control values in the integrated circuit prior to stopping the calibration clock signal.  
   
   
       5 . The method as recited in  claim 1  further comprising querying the device to verify that lock was achieved during a time the calibration clock signal was being supplied to the device.  
   
   
       6 . The method as recited in  claim 1  further comprising selecting a bandwidth of the calibration control loop to be one of at least at least a first and second bandwidth prior to supplying the calibration clock signal.  
   
   
       7 . The method as recited in  claim 1  further comprising storing a plurality of control values corresponding respectively to different output frequencies of the device.  
   
   
       8 . The method as recited in  claim 1  further comprising supplying the calibration clock determining the control value while the device, including a crystal oscillator and an integrated circuit, are in a sealed package.  
   
   
       9 . The method as recited in  claim 8  further comprising supplying the calibration clock while the integrated circuit is at different temperatures and storing information corresponding to control values determined at the different temperatures and temperature information corresponding to the different temperatures in the non-volatile memory.  
   
   
       10 . A device configured according to the method of  claim 1 .  
   
   
       11 . An apparatus comprising: 
 an integrated circuit including, 
 a controllable oscillator coupled to receive a reference frequency signal and a control value and to output a clock signal;  
 a terminal to receive a calibration clock signal;  
 a phase-locked loop circuit including the controllable oscillator, coupled to the terminal, the phase-locked loop circuit responsive to the calibration clock signal and a feedback signal from the controllable oscillator to generate a control signal to cause the controllable oscillator to lock to a multiple of the calibration clock signal; and  
 a non-volatile memory for storing a value corresponding to the control signal.  
   
   
   
       12 . The apparatus as recited in  claim 11  further comprising a sealed package and a resonating device coupled to supply the reference frequency signal, the resonating device packaged in the sealed package with the integrated circuit.  
   
   
       13 . The apparatus as recited in  claim 11  further comprising a storage location storing an indication of whether lock was achieved while the calibration clock signal was being supplied to the terminal and wherein the integrated circuit is responsive to a query to supply the indication.  
   
   
       14 . The apparatus as recited in  claim 12  wherein the resonating device is one of a crystal and a surface acoustic wave (SAW) device.  
   
   
       15 . The apparatus as recited in  claim 11  wherein a bandwidth of the phase-locked loop is selectable between at least a first and second bandwidth.  
   
   
       16 . An apparatus comprising: 
 a terminal for receiving a calibration clock signal;    a controllable oscillator coupled to receive a reference signal and generate a clock signal;    means for calibrating the apparatus utilizing the calibration clock signal by internally generating, in a phase-locked loop, one or more control values for the controllable oscillator to cause the oscillator to output a signal corresponding to the calibration clock; and    a non-volatile storage for storing one or more values corresponding to the one or more control values.    
   
   
       17 . The apparatus as recited in  claim 17  wherein the apparatus comprises an integrated circuit and a resonating device in a sealed package.  
   
   
       18 . The apparatus as recited in claim  42  wherein the controllable oscillator is a voltage-controlled oscillator.