High voltage semiconductor device and method of manufacturing the same

Abstract

A high voltage semiconductor device includes a semiconductor substrate having a high voltage well region; a device isolation film to define an active region of the semiconductor substrate; a drift region formed at an outer periphery of the device isolation film; an impurities region formed under the bottom of the drift region to cover the device isolation film; a gate electrode formed in a predetermined region of the active region; and a source/drain region formed in the drift region on either side of the gate electrode.

1 . A high voltage semiconductor device, comprising: 
 a semiconductor substrate having a high voltage well region;    a device isolation film defining an active region of the semiconductor substrate;    a drift region formed at an outer periphery of the device isolation film;    an impurities region formed under the bottom of the drift region to cover the device isolation film;    a gate electrode formed in a predetermined region of the active region; and    a source/drain region formed in the drift region on either side of the gate electrode.    
   
   
       2 . The high voltage semiconductor device of  claim 1 , wherein the impurities region is formed under the bottom of the device isolation film.  
   
   
       3 . The high voltage semiconductor device of  claim 1 , wherein a critical dimension (CD) of the gate electrode is 0.25 μm.  
   
   
       4 . The high voltage semiconductor device of  claim 1 , wherein the high voltage well region is a high voltage N-well; and the drift region formed on a surface of the high voltage well region is a low voltage P-well.  
   
   
       5 . The high voltage semiconductor device of  claim 1 , wherein the high voltage well region is a high voltage P-well; and the drift region formed on a surface of the high voltage well region is a low voltage N-well.  
   
   
       6 . The high voltage semiconductor device of  claim 1 , wherein the impurities region is an N-type impurities region formed by implanting phosphorus as high-concentration impurities.  
   
   
       7 . A method of forming a high voltage semiconductor device, the method comprising the steps of: 
 forming a high voltage well region in a semiconductor substrate;    forming a device isolation film in the semiconductor substrate;    forming a drift region on a surface of the high voltage well region;    forming an impurities region, by ion-implanting high-concentration impurities, under the bottom of the drift region to cover the device isolation film;    forming a gate electrode on the semiconductor substrate; and    forming a source/drain region on the drift region on either side of the gate electrode by ion-implanting impurities using the gate electrode as a mask.    
   
   
       8 . The method of  claim 7 , wherein the impurities region is formed under the bottom of the device isolation film.  
   
   
       9 . The method of  claim 8 , wherein the device isolation film is formed by etching the semiconductor substrate and forming a trench and depositing an insulating film in the trench.  
   
   
       10 . The method of  claim 7 , wherein a critical dimension (CD) of the gate electrode is 0.25 μm.  
   
   
       11 . The method of  claim 7 , wherein, in the step of forming the impurities region by ion-implanting high-concentration impurities under the bottom of the drift region, the impurities are ion implanted at a high energy level above 800 KeV˜900 KeV.  
   
   
       12 . The method of  claim 7 , wherein the high voltage well region is a high voltage P-well; and the drift region which is formed on a surface of the high voltage well region is a low voltage N-well.  
   
   
       13 . The method of  claim 7 , wherein the high voltage well region is a high voltage N-well; and the drift region which is formed on a surface of the high voltage well region is a low voltage P-well.  
   
   
       14 . The method of  claim 7 , wherein in the step of forming the impurities region by ion-implanting high-concentration impurities under the bottom of the drift region, phosphorus is implanted to form an N-type impurities region.  
   
   
       15 . The method of  claim 7 , the method further comprising a step of forming a silicide film on surfaces of the gate electrode and the source/drain region after forming the source/drain region.  
   
   
       16 . The method of  claim 7 , wherein the step of forming the impurities region is performed before the step of forming the device isolation film.  
   
   
       17 . The method of  claim 16 , wherein the step of forming the drift region is performed before the step of forming the impurities region.  
   
   
       18 . The method of  claim 17 , wherein the step of forming the drift region comprises a first ion implantation process at a first energy level; and 
 the step of forming the impurities region comprises a second ion implantation process at a second energy level higher than the first level.    
   
   
       19 . The method of  claim 17 , wherein, in the step of forming the device isolation film, the bottom of the device isolation film is formed to be completely covered by at least one of the impurities region and the drift region.  
   
   
       20 . The high voltage semiconductor device of  claim 1 , wherein the bottom of the device isolation film is completely covered by the impurities region.