US2007145007A1PendingUtilityA1
Semiconductor structure
Individually held — no corporate assignee on recordPriority: Jul 19, 2001Filed: Feb 15, 2007Published: Jun 28, 2007
Est. expiryJul 19, 2021(expired)· nominal 20-yr term from priority
H10W 20/093H10W 20/084H10W 20/074H10W 20/096
40
PatentIndex Score
0
Cited by
0
References
0
Claims
Abstract
This invention relates to a semiconductor structure for dual damascene processing and includes upper and lower low k dielectric layers formed in a stack when the upper surface of the lower layer has an integral etch stop layer formed by exposing the upper surfaces of the layer H 2 plasma without any prior anneal prior to the deposition of the upper layer.
Claims
exact text as granted — not AI-modified1 . A method of etching dielectric layers comprising utilizing a surface layer formed by H 2 plasma treatment of a SiCHO type material low k dielectric as an etch stop layer.
2 . The method as claimed in claim 2 wherein the etching forms part of a damascene process.Join the waitlist — get patent alerts
Track US2007145007A1 — get alerts on status changes and closely related new filings.
We store only your email — no account needed. See our privacy policy.