Method and apparatus for a deposited fill layer

Abstract

A method of forming a semiconducting wafer is provided that utilizes fewer processing operations, reduces process variation, and lowers cost as well as production time. The method provided further improves via reliability by permitting vias to be formed with consistent aspect ratios. Devices and method are provided that substantially eliminate four way intersections on semiconductor wafers between conducting elements and supplemental elements. The devices and methods provide a more uniform deposition rate of a subsequent dielectric layer. Four way intersections are removed from both conductive element regions as well as supplemental element regions.

1 . A method of fabricating a semiconductor wafer, comprising: 
 forming a pattern of elements on a semiconductor surface, including:    forming a number of conductive elements on the semiconductor surface, the conductive elements being spaced apart from each other;    wherein spaces between elements of the pattern define a number of trenches with trench axes that are substantially parallel to sides of adjacent elements of the pattern;    designing the pattern to substantially eliminate portions of the pattern where trench axes cross one another; and    filling the number of trenches using a single filling operation with a dielectric material to form a substantially planar surface.    
   
   
       2 . The method of  claim 1 , wherein designing the pattern includes designing a pattern to only include three way trench axes intersections where trenches meet at a right angle.  
   
   
       3 . The method of  claim 1 , wherein forming a pattern of elements further includes forming a number of supplemental elements in selected regions on the semiconductor surface adjacent to the number of conductive elements, the supplemental elements being spaced apart from each other and the number of conductive elements.  
   
   
       4 . The method of  claim 1 , wherein forming the number of supplemental elements includes forming a number of supplemental elements from metal.  
   
   
       5 . The method of  claim 1 , wherein forming a pattern of elements includes forming a spacing between elements in the pattern that are substantially the same between all elements.  
   
   
       6 . The method of  claim 1 , wherein filling the number of trenches using a single filling operation with a dielectric material includes a single filling operation with tetraethylorthosilicate (TEOS).  
   
   
       7 . The method of  claim 1 , wherein filling the number of trenches using a single filling operation with a dielectric material includes a single filling operation with silicon dioxide (SiO2).  
   
   
       8 . A method of fabricating a semiconductor wafer, comprising: 
 forming a pattern of elements on a semiconductor surface, including:    forming a number of conductive elements on the semiconductor surface, the conductive elements being spaced apart from each other;    wherein spaces between elements of the pattern define a number of trenches with trench axes that are substantially parallel to sides of adjacent elements of the pattern; and    designing the pattern to only include three way trench axes intersections where trenches meet at a right angle.    
   
   
       9 . The method of  claim 8 , wherein forming a pattern of elements further includes forming a number of non-conducting supplemental elements in selected regions on the semiconductor surface adjacent to the number of conductive elements, the supplemental elements being spaced apart from each other and the number of conductive elements.  
   
   
       10 . The method of  claim 9 , wherein forming a pattern of elements includes forming a spacing between elements in the pattern that are substantially the same between all elements.  
   
   
       11 . The method of  claim 10 , wherein filling the number of trenches using a single filling operation with a dielectric material includes a single filling operation with tetraethylorthosilicate (TEOS).  
   
   
       12 . The method of  claim 10 , wherein filling the number of trenches using a single filling operation with a dielectric material includes a single filling operation with silicon dioxide (SiO2).  
   
   
       13 . A method of fabricating a semiconductor wafer, comprising: 
 forming a pattern of elements on a semiconductor surface, including:    forming a number of conductive elements on the semiconductor surface, the conductive elements being spaced apart from each other;    forming a number of supplemental elements in selected regions on the semiconductor surface adjacent to the number of conductive elements, the supplemental elements being spaced apart from each other and the number of conductive elements;    wherein spaces between elements of the pattern define a number of trenches with trench axes that are substantially parallel to sides of adjacent elements of the pattern; and    filling the number of trenches using a single filling operation with a dielectric material to form a substantially planar surface.    
   
   
       14 . The method of  claim 13 , wherein forming a pattern of elements includes forming a spacing between elements in the pattern that are substantially the same between all elements.  
   
   
       15 . The method of  claim 13 , wherein designing the pattern includes designing a pattern to only include three way trench axes intersections where trenches meet at a right angle.  
   
   
       16 . The method of  claim 13 , wherein filling the number of trenches using a single filling operation with a dielectric material includes a single filling operation with tetraethylorthosilicate (TEOS).  
   
   
       17 . The method of  claim 13 , wherein filling the number of trenches using a single filling operation with a dielectric material includes a single filling operation with silicon dioxide (SiO2).