Method for fabricating semiconductor packages, and structure and method for positioning semiconductor components

Abstract

A method for fabricating semiconductor packages includes the steps of: providing a plurality of substrates and a carrier having a plurality of openings, wherein, each of the substrates has at least one chip (die) disposed thereon, length and width of the substrates are approximately equal to the predefined length and width of semiconductor packages, and length and width of the openings of the carrier are bigger than length and width of the substrates; respectively positioning the substrates in the openings of the carrier and blocking the gaps between the substrates and the carrier so as to prevent the gaps from penetrating through the carrier; performing a mold press process so as to form an encapsulant on each of the openings for encapsulating the chip, wherein length and width of the area covered by the encapsulant are bigger than length and width of the opening; performing a mold releasing process; and cutting along edges of the substrates according to the predefined length and width of semiconductor packages, thereby obtaining a plurality of semiconductor packages. The present invention also discloses a structure and method for positioning the substrates.

1 . A method for fabricating semiconductor packages, comprising the steps of: 
 preparing a plurality of substrates and a carrier having a plurality of openings, wherein, each of the substrates has at least one chip disposed thereon, the length and width of the substrates are close to the predefined length and width of the semiconductor packages, and the length and width of the openings of the carrier are bigger than the length and width of the substrates;    respectively positioning the substrates in the openings of the carrier and blocking the gaps between the substrates and the carrier so as to prevent the gaps from penetrating through the carrier;    performing a mold press process so as to form an encapsulant on each of the openings for encapsulating the chip, wherein the length and width of the area covered by each encapsulant are bigger than length and width of each opening;    performing a mold releasing process; and    cutting along edges of the substrates according to the predefined length and width of the semiconductor packages, thereby obtaining a plurality of semiconductor packages.    
   
   
       2 . The method of  claim 1  further comprising the step of mounting a plurality of solder balls on surfaces of the substrates without chips disposed thereon after the mold releasing process is performed.  
   
   
       3 . The method of  claim 1 , wherein the projection length and width of the mold cavities for forming the encapsulants are bigger than length and width of the openings.  
   
   
       4 . The method of  claim 1 , wherein an adhesive material is filled in the gaps between the substrates and the carrier so as to position the substrates in the openings.  
   
   
       5 . The method of  claim 1 , wherein at least one tape is attached to the substrates and the carrier, covering the openings and positioning the substrates in the openings, the tape being removable after the mold releasing process.  
   
   
       6 . The method of  claim 1 , wherein an adhesive material is filled in the gaps between the substrates and the carrier so as to block the gaps.  
   
   
       7 . The method of  claim 1 , wherein at least one tape is attached to the substrates and the carrier for blocking the gaps between the substrates and the carrier, the tape being removable after the mold releasing process.  
   
   
       8 . The method of  claim 1 , wherein the length and width of the substrates are 0.1 to 0.5 mm bigger than the predefined length and width of the semiconductor packages.  
   
   
       9 . The method of  claim 1 , wherein, when the length and width of the substrates are 0.1 to 0.5 mm bigger than the predefined length and width of the semiconductor packages, the length and width of the openings are 0.1 to 0.5 mm bigger than length and width of the substrates.  
   
   
       10 . The method of  claim 1 , wherein the length and width of the substrates are 0.1 to 0.5 mm smaller than the predefined length and width of the semiconductor packages.  
   
   
       11 . The method of  claim 1 , wherein, when the length and width of the substrates are 0.1 to 0.5 mm smaller than the predefined length and width of the semiconductor packages, the length and width of the openings are 0.1 to 1 mm bigger than the predefined length and width of the semiconductor packages.  
   
   
       12 . The method of  claim 1 , wherein the carrier is made of an organic dielectric material selected from the group consisting of FR4, FR5 and BT.  
   
   
       13 . The method of  claim 1 , wherein the chips are partially exposed from the encapsulants.  
   
   
       14 . The method of  claim 1 , wherein heat sinks are disposed on surfaces of the chips opposed to the substrates.  
   
   
       15 . The method of  claim 14 , wherein the heat sinks are partially exposed from the encapsulants.  
   
   
       16 . The method of  claim 1 , wherein the chips are electrically connected to the substrates through a flip-chip method.  
   
   
       17 . The method of  claim 1 , wherein the chips are electrically connected to the substrates through a wire bonding method.  
   
   
       18 . The method of  claim 1 , wherein the semiconductor packages are BGA semiconductor packages.  
   
   
       19 . A method for fabricating semiconductor packages, comprising the steps of: 
 preparing a plurality of substrates and a metallic carrier having a plurality of openings, wherein, each of the substrates has at least one chip disposed thereon, the length and width of the substrates are close to the predefined length and width of the semiconductor packages, and the length and width of the openings of the carrier are bigger than the length and width of the substrates;    respectively positioning the substrates in the openings of the metallic carrier and blocking the gaps between the substrates and the metallic carrier so as to prevent the gaps from penetrating through the metallic carrier;    performing a mold press process so as to form an encapsulant on each of the openings for encapsulating the chip, thus forming a packaged unit comprising the substrate, chip, and encapsulant, wherein the length and width of the area covered by the encapsulant are bigger than length and width of the opening;    performing a mold releasing process;    separating the package units from the metallic carrier; and    cutting along edges of the substrates of the package units according to the predefined length and width of semiconductor packages, thereby obtaining a plurality of semiconductor packages.    
   
   
       20 . The method of  claim 19 , wherein the metallic carrier is made of Cu.  
   
   
       21 . The method of  claim 19 , wherein a metal plated layer having poor adhesion with the encapsulant is formed on the metallic carrier.  
   
   
       22 . The method of  claim 21 , wherein the metal plated layer is one of the group consisting of Au, Ni and Cr.  
   
   
       23 . The method of  claim 19 , further comprising the step of mounting a plurality of solder balls on surfaces of the substrates without chips disposed thereon after the mold releasing process is performed.  
   
   
       24 . The method of  claim 19 , wherein the projection length and width of the mold cavities for forming the encapsulants is larger than the length and width of the openings.  
   
   
       25 . The method of  claim 19 , wherein an adhesive material is filled in the gaps between the substrates and the carrier so as to position the substrates in the openings.  
   
   
       26 . The method of  claim 19 , wherein at least one tape is attached to the substrates and the carrier, covering the openings and positioning the substrates in the openings, the tape being removable after the mold releasing process.  
   
   
       27 . The method of  claim 19 , wherein an adhesive material is filled in the gaps between the substrates and the carrier so as to block the gaps.  
   
   
       28 . The method of  claim 19 , wherein at least one tape is attached to the substrates and the carrier for blocking the gaps between the substrates and the carrier, the tape being removable after the mold releasing process.  
   
   
       29 . The method of  claim 19 , wherein length and width of the substrates are 0.1 to 0.5 mm bigger than the predefined length and width of the semiconductor packages.  
   
   
       30 . The method of  claim 19 , wherein, when length and width of the substrates are 0.1 to 0.5 mm bigger than predefined length and width of the semiconductor packages, the length and width of the openings are 0.1 to 0.5 mm bigger than length and width of the substrates.  
   
   
       31 . The method of  claim 19 , wherein the length and width of the substrates are 0.1 to 0.5 mm smaller than predefined length and width of the semiconductor packages.  
   
   
       32 . The method of  claim 19 , wherein, when length and width of the substrates are 0.1 to 0.5 mm smaller than predefined length and width of the semiconductor packages, the length and width of the openings are 0.1 to 1 mm bigger than predefined length and width of the semiconductor packages.  
   
   
       33 . The method of  claim 19 , wherein the chips are partially exposed from the encapsulants.  
   
   
       34 . The method of  claim 19 , wherein heat sinks are disposed on surfaces of the chips opposed to the substrates.  
   
   
       35 . The method of  claim 34 , wherein the heat sinks are partially exposed from the encapsulants.  
   
   
       36 . The method of  claim 19 , wherein the chips are electrically connected to the substrates through a flip-chip method.  
   
   
       37 . The method of  claim 19 , wherein the chips are electrically connected to the substrates through a wire bonding method.  
   
   
       38 . The method of  claim 19 , wherein the semiconductor packages are BGA semiconductor packages.  
   
   
       39 . A method for fabricating semiconductor packages, the method comprising: 
 providing a plurality of substrates and a carrier having a plurality of openings, each of the substrates having at least one chip disposed thereon, a substrate length and width approximately equal to a predefined length and width of each of the semiconductor packages, each of the openings of the carrier having an opening length and width larger than the substrate length and width of the each of the substrates, at least a storage hole being formed at a periphery of one of the openings of the carrier;    positioning the substrates in the openings of the carrier respectively and filling into the storage hole an adhesive material, which flows in gaps between the substrates and the carrier through a capillary effect;    forming encapsulant on the openings to encapsulate the chips, area where the encapsulant is formed on each of the openings being larger than the opening length and width of the opening;    performing a mold releasing process; and    cutting along edges of the substrates according to the predefined length and width of the semiconductor packages, thereby obtaining the semiconductor packages.    
   
   
       40 . The method of  claim 39  further comprising mounting a plurality of solder balls on the substrates where the chips are not disposed after the mold releasing process is performed.  
   
   
       41 . The method of  claim 39  further comprising providing a plurality of mold cavities, for forming the encapsulant, each of the mold cavities having a projection length and width larger than the opening length and width of each of the openings.  
   
   
       42 . The method of  claim 39  further comprising attaching at least one tape to the substrates and the carrier, for covering the openings and positioning the substrates in the openings, and removing the tape after the mold releasing process.  
   
   
       43 . The method of  claim 39 , wherein at least one of the gaps is 0.05 to 0.2 mm in width.  
   
   
       44 . The method of  claim 43 , wherein the at least one of the gaps is 0.1 mm in width.  
   
   
       45 . The method of  claim 39 , wherein the carrier is made of an organic dielectric material selected from the group consisting of FR4, FR5 and BT.  
   
   
       46 . The method of  claim 39 , wherein the carrier is made of a metallic material.  
   
   
       47 . The method of  claim 39 , wherein the storage hole is disposed at a corner of each of the openings of the carrier.  
   
   
       48 . The method of  claim 39 , wherein the storage hole is disposed at a side of each of the openings of the carrier.  
   
   
       49 . A method for positioning a semiconductor component, the method comprising: 
 providing a semiconductor component and a carrier having an opening having an opening length and width larger than a semiconductor length and width of the semiconductor component;    disposing at least one storage hole at a periphery of the opening of the carrier;    disposing the semiconductor component in the opening of the carrier; and    filling into the storage hole an adhesive material, which is filled in gaps between the semiconductor component and the carrier through a capillary effect, thereby positioning the semiconductor component in the carrier.    
   
   
       50 . The method of  claim 49 , wherein at least one of the gaps is 0.05 to 0.2 mm in width.  
   
   
       51 . The method of  claim 50 , wherein the gap is 0.1 mm in width.  
   
   
       52 . The method of  claim 49 , wherein the storage hole is disposed at a corner of the opening of the carrier.  
   
   
       53 . The method of  claim 49 , wherein the storage hole is disposed at a side of the opening of the carrier.  
   
   
       54 . A carrier structure for positioning a semiconductor component, the carrier structure comprising: 
 a carrier having an opening for receiving the semiconductor component; and    at least a storage hole disposed at a periphery of the opening of the carrier, for an adhesive material to be filled in, the adhesive material, through the capillary effect, being filled in gaps between the semiconductor component and the carrier, thereby positioning the semiconductor component in the carrier.    
   
   
       55 . The carrier structure of  claim 54 , wherein at least one of the gaps is 0.05 to 0.2 mm in width.  
   
   
       56 . The carrier structure of  claim 55 , wherein the gap is 0.1 mm in width.  
   
   
       57 . The carrier structure of  claim 54 , wherein the storage hole is disposed at a corner of the opening of the carrier.  
   
   
       58 . The carrier structure of  claim 54 , wherein the storage hole is disposed at a side of the opening of the carrier.