Solid-state imaging apparatus

Abstract

A plurality of pixel sets each of 16 pixels are vertically provided successively one after another. A vertical transfer path 2 has two groups a and b of transfer electrodes 1 a , 1 b to 16 a , 16 b . Two like sequence transfer electrodes in the two electrode groups are provided for each of the pixels in each set. Each pixel is connected via a shift gate 3 to each transfer channel corresponding to each of the transfer electrodes in the electrode group a. To the transfer electrodes in the electrode group a, independent shift/transfer pulse application lead lines 4 A are connected for applying independent gate pulses to the individual shift gates in addition to transfer pulses. Common lead lines are connected to the transfer electrodes 2 a and 4 a , 5 a and 7 a , 10 a , 12 a , and 13 a and 15 a . Transfer pulse application lead lines 4B are connected to the transfer electrodes in the electrode group b. Thus, a CCD imaging device is constructed, which is capable of performing a desired read-out operation by 4-phase driving. The invention realizes a solid-state imaging device capable of reducing the numbers of lead lines for shift gate control gate electrodes for charge read-out to a vertical transfer path and external circuit connection terminals and is capable of a special read-out, such as a multiple rate read-out.

1 - 7 . (canceled)  
   
   
       8 . A solid-state imaging device comprising: 
 a pixel unit constituted by a two-dimensional array of pixels for generating charge in correspondence to received light and accumulating the charge for a predetermined period of time;    a vertical transfer unit for vertically transferring charge from the pixels in the pixel unit, a horizontal transfer unit for horizontally transferring charge from the vertical transfer unit;    shift gates each provided between each pixel and the vertical transfer unit for reading out the charge in the pixels to the vertical transfer unit, gate electrodes for controlling the shift gates; and    a plurality of lead lines for connecting the gate electrodes to an external circuit and a plurality of connection terminals for connecting the gate electrodes to the external circuit,    the gate electrodes being provided in a predetermined number N of gate electrode groups such that horizontal line number of the gate electrode groups which are connected to respective common lead lines belong to each same residue class of modulo N, N being a predetermined natural number between 4 and one half the number of pixels in a column, and N also being the minimum periodic unit of connections from said gate electrodes having the same modulo N value and belonging to different gate electrode groups to said connection terminals within said successive pixel rows, some of the gate electrode groups being commonly connected    (i) so that the connection terminals are less in number than N, and    (ii) to enable the gate electrodes having common connection terminals to be controlled with different timing from the timing of non-common connection terminals of the gate electrode groups,    wherein the commonly connected gate electrode groups are always controlled in the same way in each of all predetermined read-out modes including selective pixel read-out modes by selective shift gate driving.