Growth of GaAs expitaxial layers on Si substrate by using a novel GeSi buffer layer

Abstract

This invention provides a process for growing Ge epitaixial layers on Si substrate by using ultra-high vacuum chemical vapor deposition (UHVCVD), and subsequently growing a GaAs layer on Ge film of the surface of said Ge epitaixial layers by using metal organic chemical vapor deposition (MOCVD). The process comprises steps of, firstly, pre-cleaning a silicon wafer in a standard cleaning procedure, dipping it with HF solution and prebaking to remove its native oxide layer. Then, growing a high Ge-composition epitaixial layer, such as Si 0.1 Ge 0.9 in a thickness of 0.8 μm on said Si substrate by using ultra-high vacuum chemical vapor deposition under certain conditions. Thus, many dislocations are generated and located near the interface and in the low of part of S i0.1 Ge 0.9 due to the large mismatch between this layer and Si substrate. Furthermore, a subsequent 0.8 μm Si 0.05 Ge 0.95 layer, and/or optionally a further 0.8 μm Si 0.02 Ge 0.98 layer, are grown. They form strained interfaces of said layers can bend and terminate the propagated upward dislocation very effectively. Therefore, a film of pure Ge is grown on the surface of said epitaixial layers. Finally, a GaAs epitaixial layer is grown on said Ge film by using MOCVD.

1 - 13 . (canceled)  
     
     
         14 . The semiconductor structure of SiGe epitaxy, comprising a silicon substrate, a first SiGe epitaxial layer having Ge content at least 70 wt. %, a second SiGe epitaxial layer having Ge content more than that of the first layer, an optional third SiGe epitaxial layer having Ge content more than that of the second layer, a pure Ge film, and a GaAs epitaxial layer as the topmost layer, characterized in that the first SiGe epitaxial layer can accommodate large dislocations which are generated and located near in the low part of the first layer and the interface due to the large lattice mismatch, and the second and/or the third optional layers can form strained interfaces of said layers to bend and terminate the propagated upward dislocation very effectively.  
     
     
         15 . A semiconductor structure of SiGe eptiaxy, comprising a silicon substrate, a first SiGe epitaxial layer having Ge content at least 70 wt. %, a second SiGe epitaxial layer having Ge content more than that of the first layer, an optional third SiGe epitaxial layer having Ge content more than that of the second layer, a pure Ge film, and a GaAs epitaxial layer as the topmost layer, characterized in that the thickness of epitaxial layers totally is controlled in not exceed to 3.0 μm, and the surface of said layers is very smooth and without planarization using CMP.  
     
     
         16 . A semiconductor structure of SiGe eptiaxy, comprising a silicon substrate, a first SiGe epitaxial layer having Ge content at least 70 wt. %, a second SiGe epitaxial layer having Ge content more than that of the first layer, an optional third SiGe epitaxial layer having Ge content more than that of the second layer, a pure Ge film, and a GaAs epitaxial layer as the topmost layer, characterized in that the threading density is not controlled in not exceed to 10 6 /cm 2 .  
     
     
         17 . The semiconductor structure according to  claim 14  is suitable as high-speed devices and optical devices.  
     
     
         18 . The semiconductor structure according to  claim 14  is further suitable as a wafer of Group III-IV material and an integrating wafer which is used to integrate Group III-IV material and Group IV material.  
     
     
         19 . The semiconductor structure according to  claim 15  is suitable as high-speed devices and optical devices.  
     
     
         20 . The semiconductor structure according to  claim 16  is suitable as high-speed devices and optical devices.  
     
     
         21 . The semiconductor structure according to  claim 15  is further suitable as a wafer of Group III-IV material and an integrating wafer which is used to integrate Group III-IV material and Group IV material.  
     
     
         22 . The semiconductor structure according to  claim 16  is further suitable as a wafer of Group III-IV material and an integrating wafer which is used to integrate Group III-IV material and Group IV material.