Method for manufacturing a wafer level chip scale package

Abstract

A semiconductor wafer with semiconductor chips having chip pads and a passivation layer is provided. First and second dielectric layers are sequentially formed on the passivation layer. The first and second dielectric layers form a ball pad area that includes an embossed portion, i.e., having a non-planar surface. A metal wiring layer is formed on the resulting structure including the embossed portion. A third dielectric layer is formed on the metal wiring layer. A portion of the third dielectric layer located on the embossed portion is removed to form a ball pad. A solder ball is formed on the embossed ball pad. With the embossed ball pad, the contact area between the solder balls and the metal wiring layer is increased, thereby improving the connection reliability.

1 . A wafer level chip scale package (CSP), comprising: 
 a semiconductor chip having chip pads and a passivation layer exposing chip pads;    a first patterned dielectric layer disposed on the passivation layer; and    a second patterned dielectric layer, the first and second patterned dielectric layers exposing the chip pads,    wherein the first and second patterned dielectric layers have an embossed portion comprising a concave portion and a convex portion, the concave portion exposing a portion of the first patterned dielectric layer where a ball pad is to be formed, the convex portion being formed of the second patterned dielectric layer.    
     
     
         2 . The apparatus of  claim 1 , wherein the concave portion comprises a circle shape, and the convex portion comprises a ring shape and having a smaller diameter than the concave portion.  
     
     
         3 . The apparatus of  claim 1 , wherein the convex portion comprises a discontinuous ring shape.  
     
     
         4 . The apparatus of  claim 1 , wherein the area of the concave portion inside the convex portion is approximately equal to the area of the convex portion.