Schottky barrier tunnel transistor and method of manufacturing the same

Abstract

Provided are a Schottky barrier tunnel transistor and a method of manufacturing the same. The method includes the steps of: preparing a substrate; forming an active silicon layer on the substrate; forming a gate insulating layer on a region of the silicon layer; forming a gate electrode on the gate insulating layer; implanting ions into the silicon layer on which the gate insulating layer is not formed; and annealing the ion-implanted silicon layer. Accordingly, it is possible to manufacture the Schottky barrier tunnel transistor having stable characteristics and high performance by implanting the ions into the silicon layer using an ion implantation method and then annealing the silicon layer to form metal-silicide.

1 . A method of manufacturing a Schottky barrier tunnel transistor, the method comprising the steps of: 
 preparing a substrate;    forming an active silicon layer on the substrate;    forming a gate insulating layer on a region of the silicon layer;    forming a gate electrode on the gate insulating layer;    implanting ions into the silicon layer on which the gate insulating layer is not formed; and    annealing the ion-implanted silicon layer.    
   
   
       2 . The method according to  claim 1 , further comprising the step of, after forming the gate insulating layer, forming sidewall spacers on sidewalls of the gate insulating layer and the gate electrode.  
   
   
       3 . The method according to  claim 1 , wherein, in the step of implanting the ions into the silicon layer, one of erbium (Er), ytterbium (Yr), samarium (Sm), and yttrium (Y) is implanted when an N-type device is manufactured.  
   
   
       4 . The method according to  claim 3 , wherein the annealing is performed at a temperature of about 500° C. to 600° C.  
   
   
       5 . The method according to  claim 1 , wherein, in the step of implanting the ions into the silicon layer, platinum (Pt) is implanted when a P-type device is manufactured.  
   
   
       6 . The method according to  claim 5 , wherein the annealing is performed at a temperature of about 400° C. to 600° C.  
   
   
       7 . The method according to  claim 2 , wherein the silicon layer is formed to a thickness of about 50 nm or less.  
   
   
       8 . The method according to  claim 1 , wherein the substrate is a silicon on insulator (SOI) substrate or a bulk silicon substrate.  
   
   
       9 . The method according to  claim 8 , wherein the substrate is a substrate having a low concentration of about 10 17  cm −3  or less.  
   
   
       10 . A Schottky barrier tunnel transistor comprising: 
 an active silicon layer formed on a silicon substrate, and having source and drain regions formed of metal-silicide using ion implantation and a channel region between the source and regions;    a gate insulating layer formed on the active silicon layer; and    a gate electrode formed on the gate insulating layer.    
   
   
       11 . The Schottky barrier tunnel transistor according to  claim 10 , wherein the metal-silicide of the source and regions is formed by implanting different ions depending on an N-type device or a P-type device.  
   
   
       12 . The Schottky barrier tunnel transistor according to  claim 10 , further comprising sidewall spacers formed on sidewalls of the gate insulating layer and the gate electrode.