Jitter generation

Abstract

The present invention relates to a method for generating jitter in a digital data signal, the digital data signal having a predetermined data pattern being stored in a memory, the method comprising the steps of reading out the digital data signal from the memory using a clock signal provided by a clock source and modulating the clock signal provided by the clock source according to clock-control data, wherein the clock-control data represents the jitter to be generated in the digital data signal read out from the memory.

1 . A method for generating jitter in a digital data signal, said digital data signal having a predetermined data pattern being stored in a memory, said method comprising the steps of: 
 reading out said digital data signal from said memory using a clock signal provided by a clock source,    modulating said clock signal provided by said clock source according to clock-control data,    wherein said clock-control data represents said jitter to be generated in said digital data signal read out from said memory.    
     
     
         2 . The method of  claim 1 , wherein said step of modulating of said clock signal comprises a phase modulation.  
     
     
         3 . The method of  claim 1 , wherein said clock-control data are programmable.  
     
     
         4 . The method of  claim 1 , wherein said digital data signal having said predetermined data pattern are input in said memory using a first clock, said first clock being different from said clock signal used for read out said digital data signal from said memory.  
     
     
         5 . The method of  claim 4 , wherein said first clock is recovered from a bit stream also comprising said predetermined data pattern of said digital data signal.  
     
     
         6 . The method of  claim 1 , wherein said memory has a first-in-first-out (FIFO) architecture.  
     
     
         7 . The method of  claim 1 , wherein said step of modulating said clock signal comprising a N/M phase-locked-loop modulation of a reference clock, and/or comprising a fractional-N phase-locked-loop modulation of a reference clock, wherein N and M being integer.  
     
     
         8 . The method of  claim 1 , wherein said step of modulating said clock signal comprising a direct-digital-synthesis (DSS) modulation.  
     
     
         9 . The method of  claim 1 , wherein said step of modulating said clock signal comprising ring-oscillator modulation.  
     
     
         10 . The method of  claim 1 , wherein said digital data signal is a stimulus signal for a Device Under Test (DUT), and in that a response signal of said Device Under Test (DUT) on said stimulus signal is returned to said Automated Test Equipment (ATE) for evaluation.  
     
     
         11 . The method of  claim 10 , wherein said data pattern is provided by said Automated Test Equipment (ATE).  
     
     
         12 . The method of  claim 10 , wherein said data pattern is provided by said Device Under Test (DUT).  
     
     
         13 . A software program or product, preferably stored on a data carrier, for executing, when running on a data processing system such as a computer, a method for generating jitter in a digital data signal, said digital data signal having a predetermined data pattern being stored in a memory, said method comprising the steps of: 
 reading out said digital data signal from said memory using a clock signal provided by a clock source,    modulating said clock signal provided by said clock source according to clock-control data,    wherein said clock-control data represents said jitter to be generated in said digital data signal read out from said memory.    
     
     
         14 . A system for generating jitter in a digital data signal, said digital data signal having a predetermined data pattern being stored in a memory, said system comprising: 
 a clock source providing a clock signal used for reading out said digital data signal from said memory,    a modulator for modulating said clock signal provided by said clock source according to clock-control data,    wherein said clock-control data represents said jitter to be generated in said digital data signal read out from said memory.