Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device includes an interconnect member, a first semiconductor chip, a second semiconductor chip, a resin layer, an inorganic insulating layer, and a through electrode. The first semiconductor chip is mounted in a face-down manner on the interconnect member. The resin layer covers the side surface of the first semiconductor chip. This inorganic insulating layer is in contact with the back surface of the first semiconductor chip, and directly covers the back surface. Also, the inorganic insulating layer extends over the resin layer. The through electrode penetrates the inorganic insulating layer and the semiconductor substrate of the first semiconductor chip. The second semiconductor chip is mounted in a face-down manner on the inorganic insulating layer that covers the back surface of the first semiconductor chip in the uppermost layer.

1 . A method of manufacturing a semiconductor device, comprising: 
 forming an interconnect member;    mounting a first semiconductor chip having a semiconductor substrate in a face-down manner on said interconnect member;    forming a resin layer on said interconnect member so as to cover a side surface of said first semiconductor chip;    thinning said first semiconductor chip and said resin layer;    forming an inorganic insulating layer on a back surface of said first semiconductor chip so as to be in contact with said back surface and to extend over said resin layer; and    forming a through electrode so as to penetrate said inorganic insulating layer and said semiconductor substrate.    
     
     
         2 . The method according to  claim 1 , further comprising mounting a second semiconductor chip in a face-down manner on said inorganic insulating layer so as to be electrically connected to said through electrode.  
     
     
         3 . The method according to  claim 2 , 
 wherein said mounting of said second semiconductor chip includes mounting a plurality of said second semiconductor chips in a same layer.    
     
     
         4 . The method according to  claim 2 , 
 wherein said mounting of said second semiconductor chip includes disposing a dummy chip, which is a chip where no semiconductor element is formed, in a same layer as said second semiconductor chip.    
     
     
         5 . The method according to  claim 1 , further comprising forming an insulating ring in said semiconductor substrate so as to surround a region where said through electrode is to be formed, before said mounting of said first semiconductor chip.  
     
     
         6 . The method according to  claim 1 , 
 wherein said mounting of said first semiconductor chip includes mounting a plurality of said first semiconductor chips in a same layer.    
     
     
         7 . The method according to  claim 1 , 
 wherein said mounting of said first semiconductor chip includes disposing a dummy chip, which is a chip where no semiconductor element is formed, in a same layer as said first semiconductor chip.    
     
     
         8 . The method according to  claim 4 , 
 wherein said dummy chip is disposed so as to be spaced apart from a side surface of said semiconductor device.    
     
     
         9 . The method according to  claim 1 , 
 wherein said interconnect member is formed on a supporting substrate, and    said method further comprises removing said supporting substrate after said forming of said through electrode.    
     
     
         10 . The method according to  claim 9 , further comprising forming an external electrode terminal on a surface of said interconnect member where said supporting substrate has been disposed, after said removing of said supporting substrate.  
     
     
         11 . The method according to  claim 1 , 
 wherein said forming of said interconnect member includes forming said interconnect member on a supporting substrate, and    said method further comprises forming an external electrode terminal on a surface of said first semiconductor chip opposite to said supporting substrate, after said forming of said through electrode.    
     
     
         12 . The method according to  claim 11 , 
 wherein said supporting substrate is a device wafer.    
     
     
         13 . The method according to  claim 11 , further comprising: 
 mounting a second semiconductor chip in a face-down manner on said inorganic insulating layer so as to be electrically connected to said through electrode;    forming a resin on said inorganic insulating film so as to cover said second semiconductor chip; and    forming a via in said resin,    wherein said forming of said external electrode terminal is conducted after said forming of said via, and    said external electrode terminal is electrically connected to said through electrode through said via.    
     
     
         14 . The method according to  claim 11 , further comprising: 
 forming a conductor post on said inorganic insulating film;    mounting a second semiconductor chip in a face-down manner on said inorganic insulating layer so as to be electrically connected to said through electrode;    forming a resin on said inorganic insulating film so as to cover said conductor post and said second semiconductor chip; and    grinding said resin until said conductor post is exposed,    wherein said forming of said external electrode terminal is conducted after said grinding of said resin, and    said external electrode terminal is electrically connected to said through electrode through said conductor post.    
     
     
         15 . The method according to  claim 11 , further comprising: 
 mounting a second semiconductor chip in a face-down manner on said inorganic insulating layer so as to be electrically connected to said through electrode;    forming a resin on said inorganic insulating film so as to cover said second semiconductor chip;    adhering an adhesive layer on said resin, said adhesive layer having larger area than said resin; and    forming a via in said adhesive layer and said resin,    wherein said forming of said external electrode terminal is conducted after said forming of said via, and    said external electrode terminal is electrically connected to said through electrode through said via.    
     
     
         16 . The method according to  claim 11 , further comprising: 
 mounting a silicon interposer having a silicon substrate on an inorganic insulating film so as to be electrically connected to said through electrode;    forming a second inorganic insulating film on said silicon interposer; and    forming a second through electrode so as to penetrate said second inorganic insulating layer and said silicon substrate,    wherein said forming of said external electrode terminal is conducted after said forming of said second through electrode, and    said external electrode terminal is electrically connected to said through electrode of said first semiconductor chip through said second through electrode.    
     
     
         17 . The method according to  claim 16 , further comprising: 
 mounting a second semiconductor chip in a face-down manner on said second inorganic insulating layer so as to be electrically connected to said second through electrode;    forming a resin on said second inorganic insulating film so as to cover said second semiconductor chip; and    forming a via in said resin,    wherein said forming of said external electrode terminal is conducted after said forming of said via, and    said external electrode terminal is electrically connected to said through electrode of said first semiconductor chip through said second through electrode and said via.    
     
     
         18 . The method according to  claim 16 , further comprising: 
 forming a resin on said second inorganic insulating film without mounting a semiconductor chip; and    forming a via in said resin,    wherein said forming of said external electrode terminal is conducted after said forming of said via, and    wherein said external electrode terminal is electrically connected to said through electrode of said first semiconductor chip through said second through electrode and said via.    
     
     
         19 . The method according to  claim 16 , 
 wherein said silicon interposer is mounted so as to collectively cover an upper portion of a plurality of said first semiconductor chips.    
     
     
         20 . The method according to  claim 1 , 
 wherein said forming of said through electrode includes forming a through hole that penetrates said inorganic insulating layer and said semiconductor substrate, and filling said through hole with a metal, and    in said filling of said through hole, a seed metal is formed in an inside of said through hole and on said inorganic insulating layer by a sputtering method or a CVD method, and thereafter, electrolytic plating is carried out, and a metal formed on said inorganic insulating layer by said electrolytic plating is removed by CMP.    
     
     
         21 . The method according to  claim 1 , 
 wherein said forming of said through electrode includes forming a through hole that penetrates said inorganic insulating layer and said semiconductor substrate, and filling said through hole with a metal, and    in said filling of said through hole, a seed metal is formed in an inside of said through hole and on said inorganic insulating layer by a sputtering method, and said seed metal formed on places other than a bottom surface of said through hole is removed, and thereafter, electroless plating is carried out.    
     
     
         22 . A semiconductor device comprising: 
 an interconnect member;    a first semiconductor chip mounted in a face-down manner on said interconnect member and having a semiconductor substrate;    a resin layer provided on said interconnect member so as to cover a side surface of said first semiconductor chip;    an inorganic insulating layer provided on a back surface of said first semiconductor chip so as to be in contact with said back surface and to extend over said resin layer; and    a through electrode penetrating said first semiconductor chip and said semiconductor substrate.    
     
     
         23 . The semiconductor device according to  claim 22 , further comprising a second semiconductor chip mounted in a face-down manner on said inorganic insulating layer so as to be electrically connected to said through electrode.  
     
     
         24 . The semiconductor device according to  claim 23 , 
 wherein a plurality of said second semiconductor chips are provided in a same layer.    
     
     
         25 . The semiconductor device according to  claim 23 , 
 wherein a dummy chip, which is a chip where no semiconductor element is formed, is provided in a same layer as said second semiconductor chip.    
     
     
         26 . The semiconductor device according to  claim 22 , further comprising an insulating ring provided in said semiconductor substrate so as to surround said through electrode.  
     
     
         27 . The semiconductor device according to  claim 22 , 
 wherein a plurality of said first semiconductor chips are provided in a same layer.    
     
     
         28 . The semiconductor device according to  claim 22 , 
 wherein a dummy chip, which is a chip where no semiconductor element is formed, is provided in a same layer as said first semiconductor chip.    
     
     
         29 . The semiconductor device according to  claim 25 , 
 wherein said dummy chip is spaced apart from a side surface of said semiconductor device.    
     
     
         30 . The semiconductor device according to  claim 25 , 
 wherein a capacitance element is provided in said dummy chip, and    said dummy chip is electrically connected to said first or second semiconductor chip.    
     
     
         31 . The semiconductor device according to  claim 22 , further comprising an external electrode terminal provided on a surface of said interconnect member opposite to said first semiconductor chip.  
     
     
         32 . The semiconductor device according to  claim 22 , 
 wherein said interconnect member is provided on a supporting substrate, and    an external electrode terminal is provided on a side of said first semiconductor chip opposite to said supporting substrate.    
     
     
         33 . The semiconductor device according to  claim 32 , 
 wherein said supporting substrate is a device wafer.    
     
     
         34 . The semiconductor device according to  claim 32 , further comprising: 
 a second semiconductor chip, mounted in a face-down manner on said inorganic insulating layer and electrically connected to said through electrode;    a resin, provided on said inorganic insulating film and covering said second semiconductor chip; and    a via provided in said resin,    wherein said external electrode terminal is electrically connected to said through electrode through said via.    
     
     
         35 . The semiconductor device according to  claim 32 , further comprising: 
 a second semiconductor chip, mounted in a face-down manner on said inorganic insulating layer and electrically connected to said through electrode;    a resin, provided on said inorganic insulating film and covering said second semiconductor chip; and    a conductor post, provided in said resin and exposed in a surface of said resin,    wherein said external electrode terminal is electrically connected to said through electrode through said conductor post.    
     
     
         36 . The semiconductor device according to  claim 32 , further comprising: 
 a second semiconductor chip, mounted in a face-down manner on said inorganic insulating layer and electrically connected to said through electrode;    a resin, provided on said inorganic insulating film and covering said second semiconductor chip;    an adhesive layer adhered on said resin and having larger area than said resin; and    a via provided in said adhesive layer and said resin,    wherein said external electrode terminal is electrically connected to said through electrode through said via.    
     
     
         37 . The semiconductor device according to  claim 32 , further comprising: 
 a silicon interposer having a silicon substrate, said silicon interposer being mounted on said inorganic insulating film so as to be electrically connected to said through electrode;    a second inorganic insulating film provided on said silicon interposer; and    a second through electrode, penetrating said second inorganic insulating film and said silicon substrate,    wherein said external electrode terminal is electrically connected to said through electrode of said first semiconductor chip through said second through electrode.    
     
     
         38 . The semiconductor device according to  claim 37 , further comprising: 
 a second semiconductor chip, mounted in a face-down manner on said inorganic insulating layer and electrically connected to said through electrode;    a resin, provided on said second inorganic insulating film and covering said second semiconductor chip; and    a via provided in said resin,    wherein said external electrode terminal is electrically connected to said through electrode of said first semiconductor chip through said second through electrode and said via.    
     
     
         39 . The semiconductor device according to  claim 37 , further comprising: 
 a resin provided on said second. inorganic insulating film; and    a via provided in said resin,    wherein said external electrode terminal is electrically connected to said through electrode of said first semiconductor chip through said second through electrode and said via, and    no semiconductor chip is mounted on said second inorganic insulating film.    
     
     
         40 . The semiconductor device according to  claim 37 , 
 wherein said silicon interposer collectively covers an upper portion of a plurality of said first semiconductor chips.