Forming a barrier layer in joint structures

Abstract

Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a barrier layer on a substrate, wherein the barrier layer comprises molybdenum; and forming a lead free interconnect structure on the barrier layer.

1 . A structure comprising: 
 a lead free interconnect structure disposed on a barrier layer, wherein the barrier layer comprises molybdenum.    
   
   
       2 . The structure of  claim 1  wherein the barrier layer further comprises a material selected from the group consisting of nickel, cobalt and iron.  
   
   
       3 . The structure of  claim 1  wherein the barrier layer comprises a thickness of between about 500 angstroms and about 7 microns.  
   
   
       4 . The structure of  claim 1  wherein the barrier layer comprises a molybdenum percentage of between about 5 percent and about 80 percent.  
   
   
       5 . The structure of  claim 1  wherein the lead free interconnect structure comprises tin.  
   
   
       6 . The structure of  claim 1  wherein the barrier layer is disposed on a copper substrate.  
   
   
       7 . The structure of  claim 1  wherein a wetting layer is disposed between the barrier layer and the lead free interconnect structure.  
   
   
       8 . A system comprising: 
 a lead free interconnect structure disposed on a barrier layer, wherein the barrier layer comprises molybdenum;    a bus communicatively coupled to the barrier layer; and    a DRAM communicatively coupled to the bus.    
   
   
       9 . The system of  claim 8  wherein the barrier layer further comprises a material selected from the group consisting of nickel, cobalt and iron.  
   
   
       10 . The system of  claim 8  wherein the barrier layer comprises a thickness of between about 500 angstroms and about 7 microns.  
   
   
       11 . The system of  claim 8  wherein the barrier layer comprises a molybdenum percentage of between about 5 percent and about 80 percent.  
   
   
       12 . The system of  claim 8  wherein the lead free interconnect structure comprises tin.  
   
   
       13 . The system of  claim 8  wherein the lead free interconnect structure is disposed on at least one of an interposer, a motherboard, and a package.  
   
   
       14 . The system of  claim 8  wherein the barrier layer is disposed on a copper substrate.  
   
   
       15 . The structure of  claim 8  wherein a wetting layer is disposed between the barrier layer and the lead free interconnect structure.