Semiconductor Device Equipped with a Voltage Step-Up Circuit

Abstract

A semiconductor device is equipped with a step-up circuit having a series of multiple charge pump units. Each of the units has a well separation type MOS transistor. The separation well of the transistor is coupled to a high potential so as to form double reverse biases between the N-type well and a P-type substrate and between the N-type well and a P-type well. This permits the threshold Vth of the MOS transistor to be held at low level. The units are provided with a clock whose current supply capability is limited until a predetermined condition (that a predetermined period of time has elapsed after the onset of the step-up circuit by a startup signal or that the output voltage has reached a predetermined level). This limitation of the clock facilitates suppression of power consumption by the step-up circuit during a startup, thereby reducing changes in amplitude of a supply voltage.

1 - 5 . (canceled)  
   
   
       6 . A semiconductor device equipped with a step-up circuit, said voltage step-up circuit comprising multiple charge pump units connected in series, each charge pump unit consisting of a MOS transistor and a capacitor having one end connected to the input or output end of said MOS transistor and another end connected to a clock line supplying a clock, said charge pump units adapted to step up a supply voltage in response to said clock, wherein 
 the capacitor of at least the first unit of said multiple charge pump units receiving said supply voltage is a MOS capacitor;    the capacitor of at least the last unit of said multiple charge pump units providing the output voltage is a floating type capacitor that includes a first-conduction type layer formed on a semiconductor substrate or well; a dielectric layer formed on said first-conduction type layer; and a second-conduction type layer formed on said dielectric layer.    
   
   
       7 . The semiconductor device equipped with a step-up circuit according to  claim 6 , wherein 
 said MOS capacitor has two impurity-doped regions of the same conductivity type formed in said semiconductor substrate or well, and a conduction layer formed above said two impurity-doped regions via an insulation layer, said two impurity-doped regions having a higher conductivity than that of said substrate or well.    
   
   
       8 . The semiconductor device equipped with a step-up circuit according to  claim 6 , wherein said dielectric layer is formed of either one of a nitride layer, an oxide tantalum (Ta 2 O 2 ) layer, and a nitrided titanium (TiO 2 ) layer.  
   
   
       9 . The semiconductor device equipped with a step-up circuit according to  claim 6 , wherein said dielectric layer is a three-ply layer consisting of an oxide layer sandwiched by two oxide layers.  
   
   
       10 . The semiconductor device equipped with a step-up circuit according to  claim 6 , further comprising a regulator connected to the output end of an intermediate one of said multiple series charge pump units.  
   
   
       11 . The semiconductor device equipped with a step-up circuit according to  claim 10 , wherein said regulator is a series circuit formed of a diode and a regulating capacitor, providing at the node of said diode and regulating capacitor a regulated voltage.  
   
   
       12 . A semiconductor device equipped with a step-up circuit, said voltage step-up circuit comprising: 
 multiple charge pump units connected in series, each unit including MOS transistor and a capacitor having one end connected to the input or output end of said MOS transistor and another end connected to a clock line supplying a clock, said charge pump circuit adapted to step up a supply voltage in response to said clock; and    a clock generation circuit for generating said clock in response to a startup signal, wherein    said clock generation circuit for generates and provides to said capacitors a limited current supply clock having a limited current supply capability until a predetermined condition is satisfied after the reception of said startup signal, and generates and provides to said capacitor a non-limited current supply clock having a non-limited current supply capability after said predetermined condition is satisfied.    
   
   
       13 . The semiconductor device equipped with a step-up circuit according to  claim 12 , wherein said predetermined condition is that a predetermined period of time has elapsed after the reception of said startup signal.  
   
   
       14 - 19 . (canceled)