Method of fabricating metal oxide semiconductor transistor

Abstract

A masking layer is formed over a substrate. The substrate and the masking layer are patterned to form trenches that partitions the substrate into first doping type semiconductor strips. An isolation layer is formed inside the trenches such that the surface of the isolation layer is below the upper surface of the first doping type semiconductor strips. A gate oxide layer is formed on the sidewalls of the first doping type semiconductor strips. Gates are formed over the substrate. The gates cover the masking layer above the first doping type semiconductor strips and the isolation layer inside the trenches. The gates are set in a direction perpendicular to the first doping type semiconductor strips. Spacers are formed on the sidewalls of the gates and the first doping type semiconductor strips. Second doping type source/drain regions are formed in the first doping type semiconductor strips on each side of the gates.

1 . A method of fabricating a metal oxide semiconductor (MOS) transistor, comprising the steps of: 
 providing a first doping type semiconductor substrate;    forming a masking layer over the first doping type semiconductor substrate;    forming a patterned photoresist layer over the substrate and patterning the first doping type semiconductor substrate and the masking layer using the patterned photoresist layer as a mask to form a plurality of trenches and pattern out a plurality of first doping type semiconductor strips;    forming an isolation layer inside the trenches, wherein the surface of the isolation layer is below the upper surface of the first doping type semiconductor strips;    forming a gate oxide layer over the sidewalls of the first doping type semiconductor strips;    forming a plurality of gates over the first doping type semiconductor substrate, wherein the gates cover the masking layer above the first doping type semiconductor strips and the isolation layer inside the trenches and set in a direction perpendicular to the first doping type semiconductor strips;    forming a plurality of spacers on the sidewalls of the gates and the first doping type semiconductor strips; and    forming a plurality of second doping type source/drain regions in the first doping type semiconductor strips on each side of the gates.    
   
   
       2 . The method of  claim 1 , wherein the steps for forming the MOS transistor further comprises forming a pad oxide layer between the upper surface of the first doping type semiconductor strips and the masking layer.  
   
   
       3 . The method of  claim 1 , wherein the steps for forming the isolation layer comprises: 
 forming an insulating material layer over the first doping type semiconductor substrate to fill the trenches totally and cover the masking layer;    planarizing the insulating material layer using the masking layer as a polishing stop layer; and    etching the insulating material layer to form the isolation structure using the masking layer as a mask.    
   
   
       4 . The method of  claim 1 , wherein the material constituting the isolation layer comprises silicon oxide.  
   
   
       5 . The method of  claim 1 , wherein the steps for forming the MOS transistor further comprises forming a second doping type lightly doped region in the first doping type semiconductor strips on each side of the gates.  
   
   
       6 . The method of  claim 1 , wherein the steps for forming the MOS transistor further comprises forming a silicide layer over the gates and the source/drain regions.  
   
   
       7 . The method of  claim 2 , wherein the MOS transistor further comprises an n-type MOS transistor and a p-type MOS transistor.  
   
   
       8 . The method of  claim 2 , wherein the first doping type material is a p-type material and the second doping type material is an n-type material.  
   
   
       9 . The method of  claim 2 , wherein the first doping type material is an n-type material and the second doping type material is a p-type material.