Multiple Gate Oxide Analog Circuit Architecture With Multiple Voltage Supplies and Associated Method

Abstract

An analog circuit architecture with dual gate oxides and dual voltage supplies and associated method is provided. In the analog circuit architecture, different kinds of devices/transistors with different gate oxide thicknesses are powered by different voltages, such that advantages of each device technology are mixed to enhance total performance of the analog circuit. For example, thin gate oxide 0.18 um transistors are powered by 1.8V for high speed and low power consumption, whereas thick gate oxide 0.35 um transistors are powered by 3.3V for a wider signal swing range.

1 . A multi-power multi-gate-oxide analog circuit architecture comprising: 
 a plurality of first devices powered by a first voltage; and    a plurality of second devices powered by a second voltage,    wherein the second voltage is different from the first voltage.    
   
   
       2 . The analog circuit architecture of  claim 1 , wherein the plurality of first devices is in thin-gate-oxide Metal Oxide Semiconductor (MOS) technology, the plurality of second devices is in thick-gate-oxide MOS technology, and the second voltage is higher than the first voltage.  
   
   
       3 . The analog circuit architecture of  claim 1 , wherein the plurality of first devices and the plurality of second devices are fabricated in one process but undergo different process steps.  
   
   
       4 . The analog circuit architecture of  claim 1 , wherein the architecture can process an analog signal.  
   
   
       5 . The analog circuit architecture of  claim 1 , wherein the architecture implements an analog-to-digital converter.  
   
   
       6 . The analog circuit architecture of  claim 1 , wherein the architecture implements a mixed-signal circuit.  
   
   
       7 . The analog circuit architecture of  claim 1 , wherein the architecture is implemented on a single substrate.  
   
   
       8 . A pipeline analog-to-digital converter comprising: 
 a plurality of pipeline modules, each pipeline module comprising a plurality of first devices powered by a first voltage and a plurality of second devices powered by a second voltage,    wherein the second voltage is different from the first voltage.    
   
   
       9 . The pipeline analog-to-digital converter (ADC) of  claim 8 , wherein the ADC is an analog circuit for processing an analog signal.  
   
   
       10 . The pipeline analog-to-digital converter of  claim 9 , wherein each pipeline module comprises an input circuit, an output circuit and a core circuit, the input circuit and the output circuit are formed of a first portion of the first devices and the second devices, and the core circuit is formed of a second portion of the first devices, the input circuit and the output circuit respectively receive and transmit a high-swing signal, and the core circuit is connected between the input circuit and the output circuit for signal processing of the high-swing signal received from the input circuit.  
   
   
       11 . The pipeline analog-to-digital converter of  claim 8 , wherein each pipeline module comprises a sample/hold circuit, an output amplifier and a core circuit, the sample/hold circuit and the output amplifier are formed of a first portion of the first devices and the second devices, and a core circuit is formed of a second portion of the first devices, the sample/hold circuit and the output amplifier receive and transmit a high-swing signal respectively, and the core circuit is connected between the sample/hold circuit and the output amplifier for processing the high-swing signal received from the sample/hold circuit.  
   
   
       12 . The pipeline analog-to-digital converter (ADC) of  claim 11 , wherein the core circuit comprises: 
 an ADC module for generating a digital signal based on an output signal from the sample/hold circuit;    a digital-to-analog converter (DAC) for converting the digital signal to an analog signal; and    a synthesizer for synthesizing the analog signal and the output signal of the sample/hold circuit.    
   
   
       13 . The pipeline analog-to-digital converter of  claim 11  further comprising: 
 a plurality of delay circuits corresponding to the plurality of pipeline modules, each delay circuit delaying a digital signal from the corresponding pipeline module; and    a digital error correction circuit for generating a digital output signal according to the delayed digital signals of the delay circuits.    
   
   
       14 . The pipeline analog-to-digital converter of  claim 13 , wherein each delay circuit and the error correction circuit are formed of a plurality of the first devices.  
   
   
       15 . The pipeline analog-to-digital converter of  claim 8 , wherein the first devices are thin-gate-oxide metal-oxide-semiconductor (MOS) transistors, the second devices are thick-gate-oxide MOS transistors, and the second voltage is higher than the first voltage.  
   
   
       16 . The pipeline analog-to-digital converter of  claim 8 , wherein the first devices and the second devices are formed in one process but undergo different process steps.  
   
   
       17 . The pipeline analog-to-digital converter of  claim 8 , wherein the pipeline analog-to-digital converter is implemented on a single substrate.  
   
   
       18 . A method of fabricating an analog integrated circuit (IC), the method comprising: 
 fabricating a first circuit in the analog IC; and    fabricating a second circuit in the analog IC,    wherein the first circuit and the second circuit are powered by a first power voltage and a second power voltage respectively, and the first power voltage and the second power voltage are different.    
   
   
       19 . The method of  claim 18 , wherein the first power voltage is lower than the second power voltage.  
   
   
       20 . The method of  claim 18 , wherein the first circuit comprises a plurality of first devices and the second circuit comprises a plurality of second devices.  
   
   
       21 . The method of  claim 20 , wherein the first circuit and the second circuit are fabricated with different gate oxide thickness.