Integrated Header Switch with Low-Leakage PMOS and High-Leakage NMOS Transistors

Abstract

System and method for providing power with a large on-current and small off-current to circuitry in an integrated circuit. A preferred embodiment comprises a switch for providing power to circuits in an integrated circuit made from a PMOS transistor and an NMOS transistor coupled in parallel. Each transistor's gate terminal is coupled to a separate control signal line. The PMOS transistor provides current to the circuits at high voltage supply levels while the NMOS transistor provides current to the circuits at low voltage supply levels, wherein the size of the PMOS and NMOS transistor can be changed during design to meet power requirements. Depending upon power requirements, multiple PMOS and NMOS transistors may be used. The combination of PMOS and NMOS transistors permit the use of limited fabrication processes wherein transistor widths can be limited.

1 - 14 . (canceled)  
     
     
         15 . A method for designing an integrated circuit, the method comprising: 
 specifying frequency targets for operation of logic gates within the integrated circuit;    determining currents to flow to the logic gates, the determining being based on the frequency targets; and    sizing a combination header switch that will be coupled between the logic gates and a voltage supply so that the combination header switch can provide the determined currents.    
     
     
         16 . The method of  claim 15 , wherein the combination header switch comprises a plurality of PMOS transistors coupled in parallel with a plurality of NMOS transistors, and wherein sizing the combination header switch determines the number of transistors in the plurality of PMOS transistors and the number of transistors in the plurality of NMOS transistors.  
     
     
         17 . The method of  claim 16 , wherein the frequency targets are specified for a range of voltage supply levels.  
     
     
         18 . The method of  claim 17 , wherein there are a plurality of frequency targets, and wherein the currents are determined by multiplying each frequency target with an associated voltage supply level.  
     
     
         19 . The method of  claim 16 , wherein the frequency targets are specified for a range of voltage supply levels, and wherein the sizing comprises: 
 selecting the number of PMOS transistors to provide current at high voltage supply levels; and    selecting the number of NMOS transistors to provide current at low voltage supply levels.    
     
     
         20 . The method of  claim 16  further comprising after the sizing, verifying that the combination header switch can provide the determined currents.  
     
     
         21 . The method of  claim 20 , wherein the sizing and verifying is repeated until the combination header switch can provide the determined currents.  
     
     
         22 . The method of  claim 15 , wherein the frequency targets are specified for a range of voltage supply levels, and wherein the sizing comprises: 
 determining a width and a length of the PMOS transistor to provide current at high voltage supply levels; and    determining a width and a length of the NMOS transistor to provide current at low voltage supply levels.