Semiconductor device

Abstract

The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.

1 . A semiconductor device comprising: 
 a semiconductor substrate;    a multilayer wiring structure that is formed over the semiconductor substrate and has a first and a second power supply wiring and a first wiring positioned under the first and the second power supply wiring;    a bonding pad positioned over the first and the second power supply wiring;    a first conductive layer positioned over the first and the second power supply wiring and electrically connected to the bonding pads; and    a protective element formed over the semiconductor substrate and electrically connected to the bonding pads; wherein    the first and the second power supply wiring pass through over the protective elements,    the first wiring is electrically connected to the protective elements,    a pulling-out region for the first wiring is provided between the first and the second power supply wiring, and    the first wiring is pulled out over the first and the second power supply wiring in the pulling-out region to be electrically connected to the first conductive layer.    
     
     
         2 . The semiconductor device according to  claim 1 , wherein 
 the bonding pad is arranged over the protective elements.    
     
     
         3 . The semiconductor device according to  claim 1 , wherein 
 the first and the second power supply wiring are different from each other in electric potential.    
     
     
         4 . The semiconductor device according to  claim 3 , wherein 
 one of the first and the second power supply wiring is a grounding wiring.    
     
     
         5 . The semiconductor device according to  claim 1 , wherein 
 the bonding pad is formed of a part of the first conductive layer.    
     
     
         6 . The semiconductor device according to  claim 1 , wherein 
 the bonding pad is electrically connected to the first and the second power supply wiring through an input/output circuit, and the protective elements constitute the input/output circuit.    
     
     
         7 . The semiconductor device according to  claim 6 , wherein 
 the bonding pad is for inputting and outputting signals.    
     
     
         8 . The semiconductor device according to  claim 6 , wherein 
 the input/output circuit includes a first and a second MISFET element, a first and a second resistance element and a first and a second diode element, and    a region where the first MISFET element is formed, a region where the first resistance element is formed, a region where the first diode is formed, a region where the pulling-out region is formed, a region where the second diode is formed, a region where the second resistance element is formed, and a region where the second MISFET element is formed are arranged in this order on the main surface of the semiconductor substrate.    
     
     
         9 . The semiconductor device according to  claim 8 , wherein 
 the first and the second power supply wiring extend along the periphery of the semiconductor device, and    a region where the first MISFET element is formed, a region where the first resistance element is formed, a region where the first diode is formed, a region where the pulling-out region is formed, a region where the second diode is formed, a region where the second resistance element is formed, and a region where the second MISFET element is formed are arranged in this order in the direction intersecting with the direction to which the first and the second power supply wiring extend.    
     
     
         10 . The semiconductor device according to  claim 8 , wherein 
 the protective elements are the first and the second resistance element and the first and the second diode element.    
     
     
         11 . The semiconductor device according to  claim 1  further comprising a first and a second MISFET element, a first and a second resistance element and a first and a second diode element formed on the semiconductor substrate and constituting an input/output circuit, wherein 
 the bonding pad is connected to the first power supply wiring through the first diode element,    the bonding pad is connected to the second power supply wiring through the second diode element,    the bonding pad is electrically connected to one of the source or the drain of the first MISFET element through the first resistance element,    the bonding pad is electrically connected to one of the source or the drain of the second MISFET element through the second resistance element,    the other of the source or the drain of the first MISFET element is connected to the first power supply wiring, and    the other of the source or the drain of the second MISFET element is connected to the second power supply wiring.    
     
     
         12 . The semiconductor device according to  claim 11 , wherein 
 the protective elements are the first and the second resistance element and the first and the second diode element.    
     
     
         13 . The semiconductor device according to  claim 11 , wherein 
 the first and the second power supply wiring extend along the periphery of the semiconductor device, and    a region where the first MISFET element is formed, a region where the first resistance element is formed, a region where the first diode is formed, a region where the pulling-out region is formed, a region where the second diode is formed, a region where the second resistance element is formed, and a region where the second MISFET element is formed are arranged in this order in the direction intersecting with the direction to which the first and the second power supply wiring extend.    
     
     
         14 . The semiconductor device according to  claim 1 , wherein 
 a plurality of the bonding pads are staggered along the periphery of the main surface the semiconductor device.    
     
     
         15 . A semiconductor device comprising: 
 a semiconductor substrate;    a multilayer wiring structure that is formed over the semiconductor substrate and has a third and a fourth power supply wiring and a first wiring positioned under the third and the fourth power supply wiring;    a bonding pad positioned over the third and the fourth power supply wiring;    a first conductive layer positioned over the third and the fourth power supply wiring and electrically connected to the bonding pad; and    protective elements formed over the semiconductor substrate and electrically connected to the bonding pad; wherein    the protective elements include MISFET elements,    the MISFET elements are formed in a first and a second MISFET forming region,    the first wiring is electrically connected to the protective elements,    a pulling-out region for the first wiring is provided between the first and the second MISFET forming region, and    the first wiring is pulled out over the third and the fourth power supply wiring in the pulling-out region to be electrically connected to the first conductive layer.    
     
     
         16 . The semiconductor device according to  claim 15 , wherein 
 the bonding pad exists over the protective elements.    
     
     
         17 . The semiconductor device according to  claim 15 , wherein 
 the protective elements further include diode elements,    the diode elements are formed in a first and a second diode element forming region, and    the pulling-out region is provided between the first nMISFET and diode element forming regions and the second nMISFET and diode element forming regions.    
     
     
         18 . The semiconductor device according to  claim 15 , wherein 
 the first wiring is electrically connected to the third power supply wiring, and to the fourth power supply wiring through the protective elements.    
     
     
         19 . The semiconductor device according to  claim 18 , wherein 
 one of the third and the fourth power supply wiring is a grounding wiring and the other is different from the grounding wiring in electric potential.    
     
     
         20 . The semiconductor device according to  claim 19 , wherein 
 the bonding pad is for supplying power supply electric potential or grounding electric potential.