Semiconductor integrated circuit

Abstract

To provide a test technology capable of reducing a package size by reducing a number of terminals (pins) in a semiconductor integrated circuit of SIP or the like constituted by mounting a plurality of semiconductor chips to a single package, in SIP 102 constituted by mounting a plurality of semiconductor chips to a signal package of ASIC 100 , SDRAM 101 and the like, a circuit of testing SDRAM 101 (SDRAMBIST 109 ) is provided at inside of ASIC 100 , and SDRAM 101 is tested from outside of SDRAM 101 , that is, from ASIC 100 . By providing the test circuit of SDRAM 101 at inside of ASIC 100 , it is not necessary to extrude a terminal for testing SDRAM 101 to outside of SIP 102.

1 . A semiconductor device which includes a first semiconductor chip and a second semiconductor chip on a single package, 
 the first semiconductor chip including a test circuit for testing the second semiconductor chip,    the first semiconductor chip including:    an input/output buffer having a control signal input and    a first terminal coupled to the input/output buffer,    the second semiconductor chip including:    a second terminal coupled to the first terminal, and 
 the input/output buffer adapted to carry out an operation of charging or discharging the first terminal and the second terminal, bringing the first terminal and the second terminal into a high impedance state and detecting voltage levels of the first terminal and the second terminal after elapse of a predetermined time period.  
   
     
     
         2 . The semiconductor device according to  claim 1 , wherein the first semiconductor chip further includes: 
 a third terminal for outputting a detecting signal of the voltage levels of the first terminal and the second terminal detected by the input/output buffer, and    wherein the third terminal is coupled to the external terminal of the single package.    
     
     
         3 . The semiconductor device according to  claim 1 , 
 wherein the first semiconductor chip further includes means for maintaining the detecting signal of the voltage levels of the first terminal and the second terminal detected by the input/output buffer.    
     
     
         4 . The semiconductor device according to  claim 1 , 
 wherein the first semiconductor chip is a system chip, and    wherein the second semiconductor chip is a memory chip.