Transistor having recess gate structure and method for fabricating the same

Abstract

A transistor having a recess gate structure and a method for fabricating the same. The transistor includes a gate insulating layer formed on the inner walls of first trenches formed in a semiconductor substrate; a gate conductive layer formed on the gate insulating layer for partially filling the first trenches; gate electrodes formed on the gate conductive layer for completely filling the first trenches, and surrounded by the gate conductive layer; channel regions formed in the semiconductor substrate along the first trenches; and source/drain regions formed in a shallow portion of the semiconductor substrate.

1 . A transistor having a recess gate structure comprising: 
 a gate insulating layer formed on inner walls of first trenches formed in a semiconductor substrate;    a gate conductive layer formed on the gate insulating layer for partially filling the first trenches;    gate electrodes formed on the gate conductive layer for completely filling the first trenches, and surrounded by the gate conductive layer;    channel regions formed in the semiconductor substrate along the first trenches; and    source/drain regions formed in a shallow portion of the semiconductor substrate and separated from the upper portions of the first trenches by the channel regions.    
   
   
       2 . The transistor of  claim 1 , wherein the gate insulating layer is an oxide layer, the gate conductive layer is a polysilicon layer, and the gate electrodes are made of a metal layer.  
   
   
       3 . The transistor of  claim 1 , wherein the surfaces of the source/drain regions are located at the same level as the surfaces of the gate conductive layer and the gate electrodes.  
   
   
       4 . The transistor of  claim 1 , further comprising a capping layer pattern formed on the gate conductive layer and the gate electrodes for selectively exposing the surfaces of the gate electrodes.  
   
   
       5 . The transistor of  claim 4 , wherein the capping layer pattern includes a nitride layer.  
   
   
       6 . A method for fabricating a transistor having a recess gate structure comprising: 
 forming first trenches having a designated depth in a semiconductor substrate;    forming channel regions in the semiconductor substrate having the first trenches formed therein along the first trenches by ion implantation;    forming a gate insulating layer on the semiconductor substrate having the channel regions formed therein;    forming a gate conductive layer on the gate insulating layer, to form second trenches in the first trenches;    forming gate electrodes filling the second trenches;    partially removing the upper portions of the gate electrode, the gate conductive layer, and the semiconductor substrate by planarization; and    implanting impurity ions into the semiconductor substrate exposed by the planarization, to form source/drain regions.    
   
   
       7 . The method of  claim 6 , wherein the depth of the first trenches 2,000 Å or less.  
   
   
       8 . The method of  claim 6 , further comprising cleaning the semiconductor substrate using CFO 2  or CF 4  gas after forming the first trenches.  
   
   
       9 . The method of  claim 6 , further comprising forming a liner oxide layer after forming the first trenches.  
   
   
       10 . The method of  claim 6 , further comprising performing an annealing process after forming the first trenches.