US2007117387A1PendingUtilityA1

Semiconductor device and manufacturing method thereof

Assignee: KIM RAE SUNGPriority: Nov 26, 2003Filed: Jan 16, 2007Published: May 24, 2007
Est. expiryNov 26, 2023(expired)· nominal 20-yr term from priority
Inventors:Rae Sung Kim
H10W 20/098H10W 20/077H10W 20/074H10W 20/47H10W 20/092H10P 95/06H10P 14/6924
44
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

The semiconductor device fabrication method of the present invention includes forming metal wirings on a semiconductor substrate, forming a first blocking layer on the semiconductor substrate and the metal wiring, forming a first FSG on the first blocking layer, forming a second blocking layer on the first FSG, forming a second FSG on the second blocking layer, and forming a protection layer on the second FSG.

Claims

exact text as granted — not AI-modified
1 . A method for fabricating semiconductor device comprising: 
 forming metal wirings on a semiconductor substrate;    forming a first blocking layer on the semiconductor substrate and the metal wirings;    forming a first FSG layer on the first blocking layer;    forming a second blocking layer on the first inter-metal dielectric layer;    forming a second inter-metal dielectric layer on the second blocking layer; and    forming a protection layer on the second inter-metal dielectric layer.    
   
   
       2 . The method of  claim 1 , wherein the first blocking layer, the first inter-metal dielectric layer, the second blocking, and the second inter-metal dielectric layer are formed using a single equipment.  
   
   
       3 . The method of  claim 2 , wherein the first and second blocking layer comprise USG.  
   
   
       4 . The method of  claim 1 , wherein the first and the second blocking layers each have a thickness in the range from 30 to 2000 Å.  
   
   
       5 . The method of  claim 2 , wherein the first and the second blocking layers each have a thickness in the range from 30 to 2000 Å.  
   
   
       6 . The method of  claim 3 , wherein the first and the second blocking layers each have a thickness in the range from 30 to 2000 Å.  
   
   
       7 . The method of  claim 1 , further comprising: 
 planarizing the protection layer;    forming contact holes penetrating the protection layer, the second inter-metal dielectric layer, the second blocking layer, the first inter-metal dielectric layer, and the first blocking layer; and    forming a wiring layer on the protection layer, the wiring layer connecting to the metal wirings through the contact holes.    
   
   
       8 . The method of  claim 2 , further comprising: 
 planarizing the protection layer;    forming contact holes penetrating the protection layer, the second inter-metal dielectric layer, the second blocking layer, the first inter-metal dielectric layer, and the first blocking layer; and    forming a wiring layer on the protection layer, the wiring layer connecting to the metal wirings through the contact holes.    
   
   
       9 . The method of  claim 3 , further comprising: 
 planarizing the protection layer;    forming contact holes penetrating the protection layer, the second inter-metal dielectric layer, the second blocking layer, the first inter-metal dielectric layer, and the first blocking layer; and    forming a wiring layer on the protection layer, the wiring layer connecting to the metal wirings through the contact holes.    
   
   
       10 . The method of  claim 1 , further comprising: 
 forming a third blocking layer on the second inter-metal dielectric layer before forming the protection layer; and    forming a third inter-metal dielectric layer on the third blocking layer.    
   
   
       11 . The method of  claim 2 , further comprising: 
 forming a third blocking layer on the second inter-metal dielectric layer before forming the protection layer; and    forming a third inter-metal dielectric layer on the third blocking layer.    
   
   
       12 . The method of  claim 3 , further comprising: 
 forming a third blocking layer on the second inter-metal dielectric layer before forming the protection layer; and    forming a third inter-metal dielectric layer on the third blocking layer.    
   
   
       13 . The method of  claim 1 , wherein the first and the second inter-metal dielectric layer comprise FSG.  
   
   
       14 . The method of  claim 2 , wherein the first and the second inter-metal dielectric layer comprise FSG.  
   
   
       15 . The method of  claim 3 , wherein the first and the second inter-metal dielectric layer comprise FSG.  
   
   
       16 . The method of  claim 4 , wherein the first and the second inter-metal dielectric layer comprise FSG.  
   
   
       17 . The method of  claim 7 , wherein the first and the second inter-metal dielectric layer comprise FSG.  
   
   
       18 . The method of  claim 10 , wherein the first and the second inter-metal dielectric layer comprise FSG.

Join the waitlist — get patent alerts

Track US2007117387A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.