Methods of forming integrated circuit devices having a resistor pattern and plug pattern that are made from a same material

Abstract

An integrated circuit device is formed by forming a resistor pattern on a substrate. An interlayer dielectric layer is formed on the resistor pattern. The interlayer dielectric layer is patterned to form at least one opening that exposes the resistor pattern. A plug pattern is formed that fills the at least one opening and the plug pattern and resistor pattern are formed using a same material.

1 . A method of forming an integrated circuit device, comprising: 
 forming a resistor pattern on a substrate;    forming an interlayer dielectric layer on the resistor pattern;    patterning the interlayer dielectric layer to form at least one opening exposing the resistor pattern; and    forming a plug pattern that fills the at least one opening, wherein the plug pattern and the resistor pattern are comprised of a same material.    
   
   
       2 . The method of  claim 1 , further comprising: 
 forming a device isolation layer in the substrate to define an active region, the resistor pattern being formed on the device isolation layer.    
   
   
       3 . The method of  claim 1 , wherein the resistor pattern and the plug pattern comprise polysilicon.  
   
   
       4 . The method of  claim 1 , wherein patterning the interlayer dielectric layer to form the at least one opening comprises: 
 etching the interlayer dielectric layer using an etch recipe having an etch selectivity with respect to the resistor pattern and using an over-etch technique so as to expose the resistor pattern.    
   
   
       5 . The method of  claim 1 , wherein the interlayer dielectric layer comprises silicon oxide, silicon nitride, and/or silicon oxynitride.  
   
   
       6 . The method of  claim 1 , further comprising the following before forming the interlayer dielectric layer: 
 sequentially forming a gate interlayer dielectric layer and an upper conductive layer on the resistor pattern; and patterning the upper conductive layer and the gate interlayer dielectric layer to expose a portion of a top surface of the resistor pattern, the exposed portion of the resistor pattern corresponding to the at least one opening in the interlayer dielectric layer.