Material architecture for the fabrication of low temperature transistor

Abstract

A structure and method for forming a carbon-containing layer in at least a portion of the end of range regions of implanted PAI and/or doped regions. The C-containing layer/region getters defects from the implanted PAI region or doped region. Example embodiments show a C-containing layer under at FET. Other example embodiments show an implanted C-containing regions implanted into the EOR region of implanted doped regions, such as pocket regions, S/D regions and SDE regions. Low temperature anneals can be used because the carbon-containing layer reduces defects.

1  to  14  (Canceled)  
   
   
       15 . A semiconductor structure comprising first and second regions and a carbon containing layer comprising: 
 a) a carbon containing layer in a substrate; said substrate comprised of crystalline structure including silicon;    b) a first region and a first end-of-range region in the substrate; 
 (1) said first end-of-range region is in said carbon containing layer;  
   c) a second region a second end-of-range region in the substrate; 
 (1) said second region end-of-range region in said carbon containing layer.  
   
   
   
       16 . The semiconductor structure  claim 15  wherein said carbon containing layer has a carbon concentration between 5E18 and 1E20 atom/cc.  
   
   
       17 . The semiconductor structure of  claim 15  wherein said carbon containing layer has a carbon concentration between 1E19 and 2E19 atom/cc.  
   
   
       18 . The semiconductor structure of  claim 15  wherein said first region has a first end-of-range region at least between a depth between 1.0*Rp-first region and 1.5*Rp-first region.  
   
   
       19 . The semiconductor structure of  claim 15  wherein said carbon containing layer is comprised of Si 1-y C y  alloy with y between about 0.001 and 0.005.  
   
   
       20 . The semiconductor structure of  claim 15  which further includes: said second region is deeper than said first region.  
   
   
       21 . The semiconductor structure of  claim 15  which further includes: said carbon containing layer extends from the top of the first end-of-range region to the bottom of said second end-of-range region.  
   
   
       22 . The semiconductor structure of  claim 15  said first region is a pocket region and said second region is a source/drain region and further includes a gate structure.  
   
   
       23  to  34  (Canceled)  
   
   
       35 . A device having a carbon doped region comprising: 
 a) a carbon containing layer in or on a substrate; said substrate comprised of a crystalline structure including silicon;    b) a gate structure over said substrate; a channel region in said substrate under said gate structure;    c) pocket regions and pocket EOR regions in said substrate adjacent to said gate structure; 
 (1) said pocket regions at least partially in said substrate and said carbon containing layer;  
 (2) said pocket EOR regions have a depth at least between 1.0*RP pocket  and 1.5*Rp pocket ;  
 (3) said pocket EOR regions at least partially in said carbon containing layer;  
   d) S/D extension regions in said substrate adjacent said gate structure;    e) spacers on the sidewalls of said gate structure;    f) source/drain regions and source/drain end-of-range regions in said substrate adjacent said gate structure; 
 (1) the source/drain end-of-range regions are within said carbon containing layer;  
   
   
   
       36 . The device of  claim 35  wherein said substrate is comprised of a lower strained region and a upper silicon cap; said lower strain region is comprised of Si 1-y Ge y  or Si -y C y  where y is between 0.1 and 0.3.  
   
   
       37 . The device of  claim 35  wherein said carbon containing layer is grown using an epitaxy process on the surface of said substrate; said carbon containing layer diffuses up into the Si layer and down into the substrate during subsequent heat processes thereby the carbon contain layer has a retro grade profile.  
   
   
       38 . The device of  claim 35  wherein said carbon containing layer has a carbon concentration between 5E18 and 1E20 atom/cc.  
   
   
       39 . The device of  claim 35  wherein said carbon containing layer is comprised of S 1-y C y  alloy with y between about 0.001 and 0.005.  
   
   
       40 . The device of  claim 35  wherein carbon containing layer extends at least from the pocket projected range to the bottom of the source/drain end-of-range regions.  
   
   
       41 . The device of  claim 35  wherein said source/drain EOR regions are located at least between the depths of 1.0*Rp SD  and 1.5*Rp SD ; and said carbon containing layer extends between 1.0 and 2.0 times the depth of the projected range of the source and drain regions.  
   
   
       42 . The device of  claim 35  wherein said carbon containing layer extends at least from the projected range of the S/D extension region to the bottom of the source/drain end-of-range regions.  
   
   
       43  to  72  (Canceled)