US2007114609A1PendingUtilityA1
Semiconductor substrate and method of manufacturing the same
Est. expiryFeb 4, 2018(expired)· nominal 20-yr term from priority
H10P 90/1914H10W 10/181H10P 90/1906H10P 95/00Y10T156/1052Y10T156/10Y10T156/1043
52
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Claims
Abstract
A method of manufacturing a semiconductor substrate can effectively prevent a chipping phenomenon and the production of debris from occurring in part of the insulation layer and the semiconductor by removing a outer peripheral portion of the semiconductor substrate so as to make the outer peripheral extremity of the insulation layer to be located between the outer peripheral extremity of the semiconductor layer and that of the support member and hence the semiconductor layer and the insulation layer produce a stepped profile.
Claims
exact text as granted — not AI-modified1 .- 15 . (canceled)
16 . An SOI wafer comprising a support member, an insulation layer arranged on the support member and a semiconductor layer arranged on the insulation layer,
wherein the outer peripheral extremity of said semiconductor layer is located inside the outer peripheral extremity of said support member, and the outer peripheral extremity of said insulation layer is located between the outer peripheral extremity of said semiconductor layer and the outer peripheral extremity of said support member, so that the outer peripheral portion of the SOI wafer, including said insulation layer and said semiconductor layer, shows a stepped profile, wherein said insulation layer has a terrace on the upper surface of the outer peripheral portion wherein the offset between the bottom of the outer peripheral extremity of said semiconductor layer and the top of the outer peripheral extremity of said insulation layer is not smaller than 2 μm, and wherein the angle of inclination formed between the lateral surface of the outer peripheral portion of said insulation layer and the bottom surface of the insulation layer is not greater than 45°.
17 . An SOI wafer according to claim 16 , wherein the lateral surface of the outer peripheral portion of said semiconductor layer also is inclined.Join the waitlist — get patent alerts
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