Thin film transistor including a lightly doped amorphous silicon channel layer

Abstract

A thin film transistor (TFT) is provided. The thin film transistor (TFT) comprises a substrate, a gate, an inter-gate dielectric layer, a channel layer and source/drain regions. A gate is formed over the substrate. An inter-gate dielectric layer is formed over the substrate covering the gate. A doped amorphous silicon layer is formed over a portion of the inter-gate dielectric layer at least covering the gate to serve as channel layer. Source/drain regions are formed over the channel layer.

1 . A thin film transistor (TFT), comprising: 
 a substrate;    a gate, disposed over the substrate;    an inter-gate dielectric layer, disposed over the substrate covering the gate;    a channel layer, disposed over a portion of the inter-gate dielectric layer, at least over the gate, wherein the channel layer comprises a lightly doped amorphous silicon layer; and    source/drain regions, disposed over the channel layer, wherein the source/drain regions are separated by a distance.    
   
   
       2 . The thin film transistor (TFT) of  claim 1 , wherein the channel layer comprises an N-type lightly doped amorphous silicon layer.  
   
   
       3 . The thin film transistor (TFT) of  claim 1 , wherein the channel layer comprises a P-type lightly doped amorphous silicon layer.  
   
   
       4 . The thin film transistor (TFT) of  claim 1 , wherein the channel layer is doped with phosphorous atoms, and a concentration of phosphorous atoms is in a range of about 1E17 atom/cm 3  to about 1E18 atom/cm 3 .  
   
   
       5 . The thin film transistor (TFT) of  claim 1 , wherein the channel layer is doped with boron atoms, and a concentration of boron atoms is in a range of about 1E16 atom/cm 3  to about 5E17 atom/cm 3 .  
   
   
       6 . The thin film transistor (TFT) of  claim 1 , wherein the lightly doped amorphous silicon layer comprises: 
 a first lightly doped sub-amorphous silicon layer, disposed over a portion of the inter-gate dielectric layer; and    a second lightly doped sub-amorphous silicon layer, disposed over the first lightly doped sub-amorphous silicon layer, wherein the first lightly doped sub-amorphous silicon layer is formed at a first deposition rate, and the second lightly doped sub-amorphous silicon layer is formed at a second deposition rate higher than the first deposition rate.    
   
   
       7 . The thin film transistor (TFT) of  claim 1 , further comprising an ohmic contact layer between the channel layer and the source/drain regions.  
   
   
       8 . The thin film transistor (TFT) of  claim 1 , further comprising a protection layer over the substrate, wherein the protection layer covers the source/drain regions, the channel layer and the inter-gate dielectric layer.