Scan testing system, method and apparatus

Abstract

Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.

1 . An integrated circuit comprising: 
 A. first and second die pads;    B. core circuitry having core input leads and core output leads; and    C. a first buffer having an input lead connected to a first core output lead, a tri-state enable lead, and an output lead connected to the first die pad;    D. a second buffer having an input lead and an output lead connected between the second die pad and one of a core input lead and a second core output lead; and    E. comparator circuitry having a core input lead connected to the first core output lead, a test enable lead connected to the tri-state enable lead, an expected data input lead connected to one of the first die pad and the second die pad, and a mask data input lead connected to the other of the first die pad and the second die pad.    
   
   
       2 . The integrated circuit of  claim 1  in which the comparator circuitry includes a scan input lead, a scan output lead, a scan control input lead and a compare strobe input lead.  
   
   
       3 . The integrated circuit of  claim 1  in which the expected data input is connected to the first die pad and the mask data input is connected to the second die pad.  
   
   
       4 . The integrated circuit of  claim 1  in which the mask data input is connected to the first die pad and the expected data input is connected to the second die pad  
   
   
       5 . The integrated circuit of  claim 1  in which the second buffer is an input buffer and the mask data input is connected to the second die pad through the second buffer.  
   
   
       6 . The integrated circuit of  claim 1  in which the second buffer is an input buffer and the expected data input is connected to the second die pad through the second buffer.