Data processor

Abstract

A data processor has a first bus master module, first bus slave module and first bus right arbitrating circuit connected to a first bus, a second bus master module, second bus slave module and second bus right arbitrating circuit connected to a second bus, and a bus bridge circuit connecting the first and second buses. The bus bridge circuit has a first transfer controller, responsive to an access request from the first bus to the second bus, for obtaining a bus right of the second bus, and a second transfer controller, responsive to an access request from the second bus to the first bus, for obtaining a bus right of the first bus. The second bus has a first path connecting the second bus slave module and the first transfer controller and a second path connecting the second bus master module and the second transfer controller.

1 . A data processor comprising: 
 a first bus;    a first bus master circuit coupled to said first bus;    a first bus slave circuit coupled to said first bus;    a second bus including a first path and a second path which are operable to split;    a second bus master circuit coupled to said second bus;    a second bus slave circuit coupled to said second bus;    a bus bridge coupling to said first and second buses;    a first bus arbitrating circuit coupled to said first bus; and    a second bus arbitrating circuit coupled to said second bus,    wherein said bus bridge includes:    a first transfer controller adapted to obtain a bus right of the second bus in response to an access request from said first bus master circuit and to transfer information of the access request; and    a second transfer controller adapted to obtain a bus right of the first bus in response to an access request from said second bus master circuit and to transfer information of the access request, and    wherein the first path couples said second bus slave circuit and said first transfer controller, and the second path couples said second bus master circuit and said second transfer controller.    
   
   
       2 . The data processor according to  claim 1 , wherein said second bus is operable to split.  
   
   
       3 . The data processor according to  claim 1 , 
 wherein said second bus includes a first split bus connected to said first transfer controller, a second split bus connected to said second bus master circuit and said second transfer controller, a third split bus connected to said second bus slave circuit, and a split bus selecting circuit adapted to selectively connect either said first or second split bus to said third split bus,    wherein said first path includes said first split bus, said split bus selecting circuit, and said third split bus, and    wherein said second path includes said second split bus.    
   
   
       4 . The data processor according to  claim 1 , 
 wherein, when a bus right request via the first transfer controller and a bus right request from the second bus master circuit are conflicted with each other, said second bus arbitrating circuit is adapted to place priority on the bus right request via the first transfer controller, and    wherein said split bus selecting circuit is adapted to select connecting the first split bus to the third split bus.    
   
   
       5 . The data processor according to  claim 4 , wherein said first bus master circuit is a processor core, and said second bus master circuit is an image processing circuit.  
   
   
       6 . The new data processor according to  claim 5 , 
 wherein said first bus slave circuit is a first bus controller adapted to receive said access request of said first bus and to control a first external bus, and    wherein said second bus slave circuit is a second bus controller adapted to receive said access request of said second bus and to control a second external bus.    
   
   
       7 . The data processor according to  claim 6 , wherein the first bus controller is operable to perform the individual access control on the first external bus, and the second bus controller is operable to perform the individual access control on the second external bus.  
   
   
       8 . The data processor according to  claim 6 , wherein the bus bridge circuit includes a register, and is controlled depending on a value of said register.  
   
   
       9 . The data processor according to  claim 1 , 
 wherein said bus bridge includes a register, and    wherein said register is operable to designate an operation mode of said bus bridge.    
   
   
       10 . The data processor according to  claim 1 , 
 wherein said bus bridge is adapted to allow said first bus master circuit of said first bus to give a bus right, when a bus right request from said first bus master circuit and a bus right request from said second bus master circuit are conflicted with each other.    
   
   
       11 . The data processor according to  claim 1 , 
 wherein said second transfer controller is adapted to decode an access address, and to determine the address included in an address area a transfer request between said first bus and said second bus or not.    
   
   
       12 . The data processor according to  claim 11 , 
 wherein said second transfer controller includes a data buffer adapted to be used for data transfer between said first bus and said second bus.    
   
   
       13 . The data processor according to  claim 1 , 
 wherein said second bus arbitrating circuit is adapted to operate said access request from said first bus master circuit by priority, when said second bus arbitrating circuit receives said access request of said first bus master circuit and said access request of said second bus master circuit.