Flash memory device and method of manufacturing the same

Abstract

A flash memory device including a tunnel dielectric layer, a floating gate layer, an interlayer dielectric layer and at least two mold layers formed on a semiconductor substrate and a method of manufacturing the same are provided. By sequentially patterning the layers, a first mold layer pattern and a floating gate layer pattern aligned with each other are formed. Exposed portions of side surfaces of the first mold layer pattern are selectively lateral etched, thereby forming a first mold layer second pattern having grooves in its sidewalls. A gate dielectric layer is formed on the semiconductor substrate adjacent to the floating gate layer pattern. A control gate having a width that is determined by the grooves in the second mold layer pattern is formed on the gate dielectric layer. By removing the first mold layer second pattern, spacers are formed on sidewalls of the control gate. Exposed portions of the interlayer dielectric layer and the floating gate layer pattern are selectively etched, using the spacer as an etch mask to form a floating gate having a width defined by the widths of the groove and spacer.

1 . A flash memory device comprising: 
 a control gate disposed on a semiconductor substrate;    a plurality of spacers disposed on sidewalls of said control gate;    a floating gate disposed under said plurality of spacers aligned therewith and having a portion extending under said control gate;    a tunnel dielectric layer disposed between said floating gate and said semiconductor substrate through which charge tunneling to said floating gate occurs;    a gate dielectric layer disposed between said control gate and said semiconductor substrate and extending onto a side surface of said floating gate; and    an interlayer dielectric layer disposed on an upper surface of said floating gate between said control gate and said floating gate.    
   
   
       2 . A flash memory device comprising: 
 a control gate disposed on a semiconductor substrate;    a first and second spacer disposed on respective first and second sidewalls of said control gate;    a floating gate disposed under said first spacer aligned with said first spacer and having one portion extending under said control gate;    a lower gate disposed under said second spacer aligned with said second spacer and opposite to said first spacer on said first sidewall of said control gate;    a tunnel dielectric layer interposed between said floating gate and said semiconductor substrate and between said lower gate and said semiconductor substrate through which charge tunneling to said floating gate occurs;    a gate dielectric layer disposed between said control gate and said semiconductor substrate and extending onto a side surfaces of said floating gate; and    an interlayer dielectric layer disposed on an upper surface of said floating gate between said control gate and floating gate.    
   
   
       3 . The flash memory device as claimed in  claim 2 , wherein said first and second spacers comprise a silicon oxide layer.