Method of making a multi-bit nanocrystal memory

Abstract

A manufacturing method for an improved memory cell having a pair of non-volatile memory transistors with each transistor using a nanocrystal gate structure, the transistor pair constructed between a pair of bit line polysilicon depositions. Between the pair of non-volatile memory transistors, a word line device is interposed, allowing serial linkage of the pair of non-volatile memory transistors.

1 . A method of fabricating a nonvolatile memory cell device, the method comprising: 
 forming a nanocrystal layer over a substrate;    forming a first polysilicon layer over said nanocrystal layer;    removing a first portion of said first polysilicon layer, thereby forming a first trench in said first polysilicon layer;    removing a first portion of said nanocrystal layer, said first portion of said nanocrystal layer substantially within an area circumscribed by said first trench;    removing a second portion of said first polysilicon layer, said second portion offset from said first trench location by a distance less than a photolithography resolution limit in an optical process, thereby forming a second trench in said first polysilicon layer;    removing a second portion of said nanocrystal layer, said second portion of said nanocrystal layer substantially within an area circumscribed by said second trench, thereby forming a nanocrystal gate area having a width that is smaller than a photolithography resolution limit in an optical process; and    forming a plurality of doped areas in said substrates.    
     
     
         2 . The method of fabricating the nonvolatile memory cell device of  claim 1  wherein said nanocrystal layer has an approximate thickness between 20 Angstroms and 60 Angstroms.  
     
     
         3 . The method of fabricating the nonvolatile memory cell device of  claim 1  wherein a tunnel oxide layer is formed before forming said nanocrystal layer and a control oxide layer is formed after forming said nanocrystal layer.  
     
     
         4 . The method of fabricating the nonvolatile memory cell device of  claim 3  wherein an average summed thickness of said tunnel oxide layer, said nanocrystal layer, and said nanocrystal layer is between approximately 120 Angstroms and 180 Angstroms.  
     
     
         5 . The method of fabricating the nonvolatile memory cell device of  claim 1  wherein the step of forming said plurality of doped areas in said substrate is performed before removing said first portion of said nanocrystal layer.  
     
     
         6 . The method of fabricating the nonvolatile memory cell device of  claim 1  wherein the step of forming said plurality of doped areas in said substrate is performed after removing said first portion of said nanocrystal layer.  
     
     
         7 . The method of fabricating the nonvolatile memory cell device of  claim 1  wherein the step of forming said plurality of doped areas in said substrate further comprises forming at least one doped area before removing said first portion of said nanocrystal layer, and forming at least one other doped area in said substrate after removing said first portion of said nanocrystal layer.  
     
     
         8 . The method of fabricating the nonvolatile memory cell device of  claim 1  wherein a second polysilicon layer is formed filling said first trench in said first polysilicon layer.  
     
     
         9 . The method of fabricating the nonvolatile memory cell device of  claim 8  wherein a third polysilicon layer is formed filling said second trench in said first polysilicon layer.  
     
     
         10 . A method for fabricating a nonvolatile dual memory cell device comprising: 
 forming a tunnel oxide layer a nanocrystal layer and a control oxide layer sequentially on a face of an underlying substrate thereby forming a nanocrystal stack layer;    forming a first polysilicon layer over said nanocrystal stack layer;    forming an oxide-nitride-oxide stack layer over said first polysilicon layer;    removing a portion of said oxide-nitride-oxide stack layer thereby forming a patterned oxide-nitride-oxide stack layer and exposing a portion of said first polysilicon layer;    removing said exposed portion of said first polysilicon layer, forming a first trench in said first polysilicon layer and exposing a first portion of said nanocrystal stack layer;    forming at least one doped area in said underlying substrate substantially beneath said first trench;    removing said first exposed portion of said nanocrystal stack layer;    forming a second polysilicon layer thereby filling said first trench in said first polysilicon layer;    removing a portion of said second polysilicon layer thereby exposing a sidewall portion of said first trench;    forming an additional oxide layer over said second polysilicon layer and over said exposed sidewall portion of said first trench;    removing a portion of said additional oxide layer using said nitride in said patterned oxide-nitride-oxide stack layer as a stop;    removing a second portion of said additional oxide layer and removing a second portion of said first polysilicon layer, said second portion of said additional oxide layer and said second portion of said first polysilicon layer being offset from said first trench location by a distance less than a photolithography resolution limit in an optical process, thereby forming a second trench in said first polysilicon layer and exposing a second portion of said nanocrystal stack layer; and    removing said exposed second portion of nanocrystal stack layer, said second portion of said nanocrystal layer substantially within an area circumscribed by said second trench thereby forming a nanocrystal gate area having a width that is smaller than a photolithography resolution limit in an optical process.    
     
     
         11 . The method of fabricating the nonvolatile memory cell device of  claim 10  wherein said nanocrystal layer has an approximate thickness between 20 Angstroms and 60 Angstroms.  
     
     
         12 . The method of fabricating the nonvolatile dual memory cell device of  claim 10  wherein an average summed thickness of said tunnel oxide layer said nanocrystal layer, and said nanocrystal layer is between approximately 120 Angstroms and 180 Angstroms.  
     
     
         13 . The method of fabricating the nonvolatile dual memory cell device of  claim 10  wherein the step of forming said at least one doped area in said underlying substrate is performed before removing said first exposed portion of said nanocrystal stack layer.  
     
     
         14 . The method of fabricating the nonvolatile dual memory cell device of  claim 10  wherein the step of forming said at least one doped area in said underlying substrate is performed after removing said first exposed portion of said nanocrystal stack layer.  
     
     
         15 . The method of fabricating the nonvolatile dual memory cell device of  claim 10  wherein forming said at least one doped area in said underlying substrate further comprises forming a doped area before removing said first exposed portion of said nanocrystal stack layer and also forming at least one other doped area after removing said first exposed portion of said nanocrystal stack layer.  
     
     
         16 . The method of fabricating the nonvolatile dual memory cell device of  claim 10  wherein a third polysilicon layer is formed thereby filling said second trench in said first polysilicon layer.