Manufacturing method of a non-volatile memory

Abstract

A non-volatile memory formed on a first conductive type substrate is provided. The non-volatile memory includes a gate, a second conductive type drain region, a charge storage layer, and a second conductive type first lightly doped region. The gate is formed on the first conductive type substrate. The second conductive type drain region is formed in the first conductive type substrate at the first side of the gate. The charge storage layer is formed on the first conductive type substrate at the first side of the gate and between the second conductive type drain region and the gate. The second conductive type first lightly doped region is formed in the first conductive type substrate at the second side of the gate. The second side is opposite to the first side.

1 . A manufacturing method of a non-volatile memory, the manufacturing method comprising: 
 providing a first conductive type substrate;    forming a gate on the first conductive type substrate;    forming a second conductive type first lightly doped region in the substrate at a first side of the gate;    forming a charge storage layer on the sidewall of the gate; and    forming a second conductive type source region in the substrate at the first side of the gate, and forming a second conductive type drain region in the substrate at a second side of the gate, wherein the second conductive type first lightly doped region is formed in the first conductive type substrate between the second conductive type source region and the gate.    
   
   
       2 . The manufacturing method as claimed in  claim 1 , wherein if the first conductive type is P-type, then second conductive type is N-type; if the first conductive type is N-type, the second conductive type is P-type.  
   
   
       3 . The manufacturing method as claimed in  claim 1 , further comprising forming a first dielectric layer on the first conductive type substrate before forming the gate on the first conductive type substrate.  
   
   
       4 . The manufacturing method as claimed in  claim 3 , wherein the first dielectric layer has a first thickness at the first side and a second thickness at the second side, and the second thickness is greater than the first thickness.  
   
   
       5 . The manufacturing method as claimed in  claim 1 , further comprising forming a second dielectric layer on the first conductive type substrate after forming the gate on the first conductive type substrate.  
   
   
       6 . The manufacturing method as claimed in  claim 1 , wherein the step of forming the second conductive type first lightly doped region in the first conductive type substrate at the first side of the gate comprises: 
 forming a patterned photoresist layer on the substrate, the patterned photoresist layer exposing the first conductive type substrate at the first side of the gate;    performing an ion implantation process to form the second conductive type first lightly doped region; and    removing the patterned photoresist layer.    
   
   
       7 . The manufacturing method as claimed in  claim 1 , further comprising forming a first conductive type lightly doped region in the substrate at the second side of the gate, the first conductive type lightly doped region being between the second conductive type drain region and the gate.  
   
   
       8 . The manufacturing method as claimed in  claim 7 , wherein the step of forming the second conductive type first lightly doped region in the first conductive type substrate at the first side of the gate and forming a first conductive type lightly doped region in the substrate at the second side of the gate comprises: 
 forming a first patterned photoresist layer on the substrate, the first patterned photoresist layer exposing the first conductive type substrate at the first side of the gate;    performing a first ion implantation process to form the second conductive type first lightly doped region;    removing the first patterned photoresist layer;    forming a second patterned photoresist layer on the substrate, the second patterned photoresist layer exposing the first conductive type substrate at the second side of the gate;    performing a second ion implantation process to form a first conductive type lightly doped region; and    removing the second patterned photoresist layer.    
   
   
       9 . The manufacturing method as claimed in  claim 7 , further comprising forming a second conductive type second lightly doped region in the substrate at the second side of the gate, the second conductive type second lightly doped region being between the second conductive type drain region and the gate.  
   
   
       10 . The manufacturing method as claimed in  claim 9 , wherein the step of forming the second conductive type first lightly doped region and the second conductive type second lightly doped region in the first conductive type substrate at the first side and the second side of the gate and forming the first conductive type lightly doped region in the substrate at the second side of the gate comprises: 
 performing a first ion implantation process to form the second conductive type first lightly doped region and the second conductive type second lightly doped region;    forming a patterned photoresist layer on the substrate, the patterned photoresist layer exposing the first conductive type substrate at the second side of the gate;    performing a second ion implantation process to form the first conductive type lightly doped region; and    removing the patterned photoresist layer.    
   
   
       11 . The manufacturing method as claimed in  claim 1 , wherein the step of forming the charge storage layer on the sidewall of the gate comprises: 
 forming a charge storage material layer on the first conductive type substrate; and    performing an anisotropic etching process to remove part of the charge storage material layer.