Single-poly non-volatile memory device and its operation method

Abstract

A single-poly, P-channel non-volatile memory cell that is fully compatible with nano-scale semiconductor manufacturing process is provided. The single-poly, P-channel non-volatile memory cell includes an N well, a gate formed on the N well, a gate dielectric layer between the gate and the N well, an ONO layer on sidewalls of the gate, a P + source doping region and a P + drain doping region. The ONO layer includes a first oxide layer deposited on the sidewalls of the gate and extends to the N well, and a silicon nitride layer formed on the first oxide layer. The silicon nitride layer functions as a charge-trapping layer.

1 . A method for erasing a single-poly, P-channel non-volatile memory unit, wherein the single-poly, P-channel non-volatile memory unit comprises an N well, a P+ source doping region, a P+ drain doping region in the N well, a P channel between the P+ source doping region and P+ drain doping region, the P channel comprising a first channel region and a second channel region that is contiguous to the first channel region and is of the same conductivity type as said first channel region; a gate dielectric layer disposed only on the first channel region; a control gate stacked on the gate dielectric layer; and a dielectric spacer comprising a floating charge trapping medium disposed on sidewalls of the control gate, wherein said charge trapping medium is situated directly above said second channel region; the method comprising: 
 connecting the control gate to a gate voltage V G      connecting the drain doping region to bias voltage V D  being positive with respect to the gate voltage V G ;    floating the source doping region; and    connecting the N well to a bias voltage V NW  being equal to the drain voltage V D  or floating the N well such that electrons trapped in the charge trapping medium are erased by means of Fowler-Nordheim tunneling (FN tunneling).    
   
   
       2 . The method according to  claim 1  wherein the dielectric spacer is an oxide-nitride-oxide (ONO) layer.  
   
   
       3 . The method according to  claim 2  wherein the ONO layer comprise a silicon oxide layer and a silicon nitride layer.  
   
   
       4 . The method according to  claim 1  wherein the control gate comprises doped polysilicon.  
   
   
       5 . The method according to  claim 1  wherein the single-poly, P-channel non-volatile memory unit does not have a lightly doped drain (LDD) near the drain side.  
   
   
       6 . The method according to  claim 1  wherein the drain voltage V D =3V˜5V.  
   
   
       7 . The method according to  claim 1  wherein the N well voltage V NW =3V˜5V.  
   
   
       8 . The method according to  claim 1  wherein the gate voltage V G =−3V˜−5V.  
   
   
       9 . A method for erasing a single-poly, P-channel non-volatile memory unit, wherein the single-poly, P-channel non-volatile memory unit comprises an N well, a P+ source doping region, a P+ drain doping region in the N well, a P channel between the P+ source doping region and P+ drain doping region, the P channel comprising a first channel region and a second channel region that is contiguous to the first channel region and is of the same conductivity type as said first channel region; a gate dielectric layer disposed only on the first channel region; a control gate stacked on the gate dielectric layer; and a dielectric spacer comprising a floating charge trapping medium disposed on sidewalls of the control gate, wherein said charge trapping medium is situated directly above said second channel region; the method comprising: 
 connecting the control gate to a gate voltage V G      connecting the drain doping region to bias voltage V D  being positive with respect to the gate voltage V G ;    floating the source doping region; and    connecting the N well to a bias voltage V NW  being positive with the drain voltage V D  such that electrons trapped in the charge trapping medium are erased by means of Band-to-Band induced Hot Hole (BBHH) injection.    
   
   
       10 . The method according to  claim 9  wherein the dielectric spacer is an oxide-nitride-oxide (ONO) layer.  
   
   
       11 . The method according to  claim 10  wherein the ONO layer comprise a silicon oxide layer and a silicon nitride layer.  
   
   
       12 . The method according to  claim 9  wherein the control gate comprises doped polysilicon.  
   
   
       13 . The method according to  claim 9  wherein the single-poly, P-channel non-volatile memory unit does not have a lightly doped drain (LDD) near the drain side.  
   
   
       14 . The method according to  claim 9  wherein the drain voltage V D =+1V˜+3V.  
   
   
       15 . The method according to  claim 9  wherein the N well voltage V NW =+3V˜+5V.  
   
   
       16 . The method according to  claim 9  wherein the gate voltage V G =−3V˜−5V.  
   
   
       17 . A method for erasing a single-poly, P-channel non-volatile memory unit, wherein the single-poly, P-channel non-volatile memory unit comprises a P substrate, an N well above the P substrate, a P+ source doping region, a P+ drain doping region in the N well, a P channel between the P+ source doping region and P+ drain doping region, the P channel comprising a first channel region and a second channel region that is contiguous to the first channel region and is of the same conductivity type as said first channel region; a gate dielectric layer disposed only on the first channel region; a control gate stacked on the gate dielectric layer; and a dielectric spacer comprising a floating charge trapping medium disposed on sidewalls of the control gate, wherein said charge trapping medium is situated directly above said second channel region; the method comprising: 
 connecting the N well to a N well voltage V NW ;    connecting the drain doping region to a drain voltage V D  being negative with respect to the N well voltage V NW  or floating the drain doping region;    floating the source doping region;    connecting the P substrate to a substrate voltage V Psub  being positive with respect to the N well voltage V NW ; and    connecting the control gate to a gate voltage V G  being negative with respect to the N well voltage V NW  such that electrons trapped in the charge trapping medium are erased by means of Substrate Hot Hole (SHH) injection.    
   
   
       18 . The method according to  claim 17  wherein the dielectric spacer is an oxide-nitride-oxide (ONO) layer.  
   
   
       19 . The method according to  claim 18  wherein the ONO layer comprise a silicon oxide layer and a silicon nitride layer.  
   
   
       20 . The method according to  claim 17  wherein the control gate comprises doped polysilicon.  
   
   
       21 . The method according to  claim 17  wherein the single-poly, P-channel non-volatile memory unit does not have a lightly doped drain (LDD) near the drain side.  
   
   
       22 . The method according to  claim 17  wherein the drain voltage V D =−1V˜−3V.  
   
   
       23 . The method according to  claim 17  wherein the N well voltage V NW =0V˜−2V.  
   
   
       24 . The method according to  claim 17  wherein the substrate voltage V Psub =1V˜2V.  
   
   
       25 . The method according to  claim 17  wherein the gate voltage V G =−3V˜−5V.  
   
   
       26 . A method for erasing a single-poly, P-channel non-volatile memory unit, wherein the single-poly, P-channel non-volatile memory unit comprises an N well, a P+ source doping region, a P+ drain doping region in the N well, a P channel between the P+ source doping region and P+ drain doping region, the P channel comprising a first channel region and a second channel region that is contiguous to the first channel region and is of the same conductivity type as said first channel region; a gate dielectric layer disposed only on the first channel region; a control gate stacked on the gate dielectric layer; and a dielectric spacer comprising a floating charge trapping medium disposed on sidewalls of the control gate, wherein said charge trapping medium is situated directly above said second channel region; the method comprising: 
 grounding the source doping region V S      connecting the drain doping region to a drain voltage V D  being negative with respect to the source voltage V S ;    connecting the N well to a N well voltage V NW  being positive with respect to the source voltage V S ; and    connecting the control gate to a gate voltage V G  being negative with respect to the source voltage V S  such that electrons trapped in the charge trapping medium are erased by means of CHannel Induced Secondary Hole Injection (CHISHI).    
   
   
       27 . The method according to  claim 26  wherein the dielectric spacer is an oxide-nitride-oxide (ONO) layer.  
   
   
       28 . The method according to  claim 27  wherein the ONO layer comprise a silicon oxide layer and a silicon nitride layer.  
   
   
       29 . The method according to  claim 26  wherein the control gate comprises doped polysilicon.  
   
   
       30 . The method according to  claim 26  wherein the single-poly, P-channel non-volatile memory unit does not have a lightly doped drain (LDD) near the drain side.  
   
   
       31 . The method according to  claim 26  wherein the drain voltage V D =−1V˜−3V.  
   
   
       32 . The method according to  claim 26  wherein the N well voltage V NW =2V˜4V.  
   
   
       33 . The method according to  claim 26  wherein the gate voltage V G =−1V˜−3V.  
   
   
       34 . A method for reading a single-poly, P-channel non-volatile memory unit, wherein the single-poly, P-channel non-volatile memory unit comprises an N well, a P+ source doping region, a P+ drain doping region in the N well, a P channel between the P+ source doping region and P+ drain doping region comprising a first channel region, a second channel region between the first channel region and the P+ drain doping region; a gate dielectric layer disposed only on the first channel region; a control gate stacked on the gate dielectric layer; and a dielectric spacer comprising a floating charge trapping medium disposed on sidewalls of the control gate, wherein said charge trapping medium is situated directly above said second channel region; the single-poly, P-channel non-volatile memory unit has a lightly doped drain (LDD) region near its source side and under the sidewall of the control gate to connect the P+ source region and the first channel; the method comprising: 
 connecting the N well to a N well voltage V NW ;    connecting the P+ drain doping region to a drain voltage V D ;    connecting the P+ source doping region to a bias source voltage V S  being negative with respect to the N well voltage V NW  to form a depletion region between the P+ source doping region and the N well; and    connecting the control gate to a bias gate voltage V G  being negative with respect to the N well voltage V NW  such that the first channel is turned on.    
   
   
       35 . The method according to  claim 34  wherein the dielectric spacer is an oxide-nitride-oxide (ONO) layer.  
   
   
       36 . The method according to  claim 35  wherein the ONO layer comprise a silicon oxide layer and a silicon nitride layer.  
   
   
       37 . The method according to  claim 34  wherein the control gate comprises doped polysilicon.  
   
   
       38 . The method according to  claim 34  wherein the single-poly, P-channel non-volatile memory unit does not have a lightly doped drain (LDD) near the drain side.  
   
   
       39 . The method according to  claim 34  wherein the source voltage V S =−1V˜−1.2V.  
   
   
       40 . The method according to  claim 34  wherein the gate voltage V G =−−1V˜−3.3V.  
   
   
       41 . The method according to  claim 34  wherein the N well is grounded.  
   
   
       42 . The method according to  claim 34  wherein the drain voltage V D =0V.  
   
   
       43 . A method for reading a single-poly, P-channel non-volatile memory unit, wherein the single-poly, P-channel non-volatile memory unit comprises an N well, a P+ source doping region, a P+ drain doping region in the N well, a P channel between the P+ source doping region and P+ drain doping region comprising a first channel region, a second channel region between the first channel region and the P+ drain doping region, and a third channel between the first channel and the P+ source doping region; a gate dielectric layer disposed only on the first channel region; a control gate stacked on the gate dielectric layer; and a dielectric spacer comprising a floating charge trapping medium disposed on sidewalls of the control gate, wherein said charge trapping mediums are situated directly above said second and third channel region; wherein electrons are injected into charge storage medium at a source side of the single-poly, P-channel non-volatile memory unit in advance to inverse the third channel; the method comprising: 
 connecting the N well to a N well voltage V NW ;    connecting the P+ drain doping region to a drain voltage V D ;    connecting the P+ source doping region to a bias source voltage V S  being negative with respect to the N well voltage V NW  to form a depletion region between the P+ source doping region and the N well; and    connecting the control gate to a bias gate voltage V G  being negative with respect to the N well voltage V NW  such that the first channel is turned on.    
   
   
       44 . The method according to  claim 43  wherein the dielectric spacer is an oxide-nitride-oxide (ONO) layer.  
   
   
       45 . The method according to  claim 44  wherein the ONO layer comprise a silicon oxide layer and a silicon nitride layer.  
   
   
       46 . The method according to  claim 43  wherein the control gate comprises doped polysilicon.  
   
   
       47 . The method according to  claim 43  wherein the single-poly, P-channel non-volatile memory unit does not have a lightly doped drain (LDD).  
   
   
       48 . The method according to  claim 43  wherein the source voltage V S =−1V˜−1.2V.  
   
   
       49 . The method according to  claim 43  wherein the gate voltage V G =−−1V˜−3.3V.  
   
   
       50 . The method according to  claim 43  wherein the N well is grounded.  
   
   
       51 . The method according to  claim 43  wherein the drain voltage V D =0V.