Charge pump

Abstract

A charge pump has a number of serially connected pumping stages, with each stage having a pair of cross coupled inverters having a first input and a second input. Each inverter has a N channel transistor having a first end and a second end, and a P channel transistor having a first end and a second end with the first end of the N channel transistor connected to the first end of the P channel transistor. A first capacitor having a first end is connected to the first input and receives a first clock signal at a second end. A second capacitor, different in size from the first capacitor, having a first end is connected to the second input and receives a second clock signal at a second end. The second end of the P channel transistor of one of the inverters is connected to the second end of the N channel transistor of one of the inverters of an adjacent stage. The second end of the P channel transistor of another of the inverters is connected to the second end of the N channel transistor of another of the inverters of an adjacent stage.

1 . A charge pump comprising: 
 a plurality of like stages, connected in series, each stage comprising:    a pair of cross coupled inverters having a first input and a second input, wherein each inverter comprising a N channel transistor having a first end and a second end, and a P channel transistor having a first end and a second end with said first end of said N channel transistor connected to the first end of said P channel transistor;    a first capacitor having a first end connected to said first input and for receiving a first clock signal at a second end;    a second capacitor, different in size from said first capacitor, having a first end connected to said second input and for receiving a second clock signal at a second end;    wherein said second end of said P channel transistor of one of said inverters is connected to the second end of said N channel transistor of one of said inverters of an adjacent stage; and    wherein said second end of said P channel transistor of another of said inverters is connected to the second end of said N channel transistor of another of said inverters of an adjacent stage.    
   
   
       2 . The charge pump of  claim 1  wherein said first clock signal supplied to said second end of said first capacitor of one stage is the same signal as the second clock signal supplied to said second end of said second capacitor of an immediately connected adjacent stage.  
   
   
       3 . The charge pump of  claim 1  wherein one of said inverters has a N channel transistor and a P channel transistor, each with a gate connected together and connected to the first end of the N channel transistor of another inverter.  
   
   
       4 . The charge pump of  claim 3  wherein the other of said inverters has a N channel transistor and a P channel transistor, each with a gate connected together and connected to the first end of the N channel transistor of the one inverter.  
   
   
       5 . The charge pump of  claim 4  wherein said first capacitor is smaller in size than said second capacitor.  
   
   
       6 . The charge pump of  claim 5  wherein each of said N channel transistor and P channel transistor of one of said inverters is connected to said first end of said first capacitor, and is smaller in size than the N channel transistor and P channel transistor of the other inverter.  
   
   
       7 . The charge pump of  claim 6 , wherein said plurality of like stages has a first stage and a last stage, wherein said second ends of said N channel transistors of said first stage is connected to a voltage source of Vdd.  
   
   
       8 . The charge pump of  claim 6 , further comprising: 
 a final inverter comprising a N channel transistor, having a first end and a second end, and a P channel transistor having a first end and a second end, each with a gate connected together, and with the first end of the N channel transistor connected to the first end of the P channel transistor;    a final N channel transistor having a first end and a second end, and a gate, with the gate connected to the first end of the N channel transistor of said final inverter, and with the first end connected to the gates of said N channel transistor and P channel transistor of said final inverter;    a first capacitor having a first end connected to said first end of said N channel transistor and P channel transistor of said final inverter, and for receiving a first clock signal at a second end;    a second capacitor, different in size from said first capacitor, having a first end connected to said first end of said final N channel transistor and for receiving a second clock signal at a second end;    a final capacitor;    wherein said second end of said P channel transistor is connected to said final capacitor; and    wherein said second end of said P channel transistor of said final stage is connected to the second end of said N channel transistor and second end of said final N channel transistor, respectively.